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/bsp/samd21/sam_d2x_asflib/common/services/adp/
A Dadp.c72 index++; in adp_add_send_byte()
75 index++; in adp_add_send_byte()
78 return index; in adp_add_send_byte()
349 uint16_t index = 0; in adp_configure_info() local
391 uint16_t index = 0; in adp_configure_stream() local
434 uint16_t index = 0; in adp_toggle_stream() local
837 index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->x, 2); in adp_add_dashboard_element_common_send_byte()
843 return index; in adp_add_dashboard_element_common_send_byte()
1310 index = adp_add_send_byte((uint8_t*)&msg_format.data, index, \ in adp_transceive_stream()
1312 index = adp_add_send_byte((uint8_t*)&msg_format.data, index, \ in adp_transceive_stream()
[all …]
/bsp/tm4c123bsp/libraries/Drivers/
A Ddrv_gpio.c50 if (index->index == -1) in get_pin()
55 index = RT_NULL; in get_pin()
57 return index; in get_pin()
71 GPIOPinTypeGPIOInput(index ->gpioBaseAddress, index->pin); in tm4c123_pin_mode()
75 GPIOPinTypeGPIOOutput(index->gpioBaseAddress, index->pin); in tm4c123_pin_mode()
79 GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_IN); in tm4c123_pin_mode()
84 GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_IN); in tm4c123_pin_mode()
90 GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_OUT); in tm4c123_pin_mode()
105 GPIOPinWrite(index ->gpioBaseAddress, index->pin, index->pin); in tm4c123_pin_write()
109 GPIOPinWrite(index ->gpioBaseAddress, index->pin, 0); in tm4c123_pin_write()
[all …]
/bsp/microchip/samc21/bsp/hri/
A Dhri_ccl_c21.h204 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_get_SEQCTRL_SEQSEL_bf()
213 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_write_SEQCTRL_SEQSEL_bf()
216 ((Ccl *)hw)->SEQCTRL[index].reg = tmp; in hri_ccl_write_SEQCTRL_SEQSEL_bf()
237 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_read_SEQCTRL_SEQSEL_bf()
253 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_get_SEQCTRL_reg()
294 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_get_LUTCTRL_ENABLE_bit()
303 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_write_LUTCTRL_ENABLE_bit()
306 ((Ccl *)hw)->LUTCTRL[index].reg = tmp; in hri_ccl_write_LUTCTRL_ENABLE_bit()
334 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_get_LUTCTRL_EDGESEL_bit()
343 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_write_LUTCTRL_EDGESEL_bit()
[all …]
A Dhri_gclk_c21.h207 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_GENEN_bit()
216 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_GENEN_bit()
219 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_GENEN_bit()
251 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_IDC_bit()
260 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_IDC_bit()
263 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_IDC_bit()
295 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OOV_bit()
304 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_OOV_bit()
307 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_OOV_bit()
339 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OE_bit()
[all …]
A Dhri_eic_c21.h714 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_get_CONFIG_FILTEN0_bit()
723 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_write_CONFIG_FILTEN0_bit()
726 ((Eic *)hw)->CONFIG[index].reg = tmp; in hri_eic_write_CONFIG_FILTEN0_bit()
754 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_get_CONFIG_FILTEN1_bit()
763 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_write_CONFIG_FILTEN1_bit()
766 ((Eic *)hw)->CONFIG[index].reg = tmp; in hri_eic_write_CONFIG_FILTEN1_bit()
794 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_get_CONFIG_FILTEN2_bit()
803 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_write_CONFIG_FILTEN2_bit()
806 ((Eic *)hw)->CONFIG[index].reg = tmp; in hri_eic_write_CONFIG_FILTEN2_bit()
834 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_get_CONFIG_FILTEN3_bit()
[all …]
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_ccl_d51.h204 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_get_SEQCTRL_SEQSEL_bf()
213 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_write_SEQCTRL_SEQSEL_bf()
216 ((Ccl *)hw)->SEQCTRL[index].reg = tmp; in hri_ccl_write_SEQCTRL_SEQSEL_bf()
237 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_read_SEQCTRL_SEQSEL_bf()
253 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_get_SEQCTRL_reg()
294 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_get_LUTCTRL_ENABLE_bit()
303 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_write_LUTCTRL_ENABLE_bit()
306 ((Ccl *)hw)->LUTCTRL[index].reg = tmp; in hri_ccl_write_LUTCTRL_ENABLE_bit()
334 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_get_LUTCTRL_EDGESEL_bit()
343 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_write_LUTCTRL_EDGESEL_bit()
[all …]
A Dhri_gclk_d51.h222 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_GENEN_bit()
231 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_GENEN_bit()
234 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_GENEN_bit()
266 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_IDC_bit()
275 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_IDC_bit()
278 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_IDC_bit()
310 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OOV_bit()
319 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_OOV_bit()
322 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_OOV_bit()
354 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OE_bit()
[all …]
/bsp/microchip/saml10/bsp/hri/
A Dhri_ccl_l10.h204 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_get_SEQCTRL_SEQSEL_bf()
213 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_write_SEQCTRL_SEQSEL_bf()
216 ((Ccl *)hw)->SEQCTRL[index].reg = tmp; in hri_ccl_write_SEQCTRL_SEQSEL_bf()
237 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_read_SEQCTRL_SEQSEL_bf()
253 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_get_SEQCTRL_reg()
294 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_get_LUTCTRL_ENABLE_bit()
303 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_write_LUTCTRL_ENABLE_bit()
306 ((Ccl *)hw)->LUTCTRL[index].reg = tmp; in hri_ccl_write_LUTCTRL_ENABLE_bit()
334 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_get_LUTCTRL_EDGESEL_bit()
343 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_write_LUTCTRL_EDGESEL_bit()
[all …]
A Dhri_gclk_l10.h187 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_GENEN_bit()
196 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_GENEN_bit()
199 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_GENEN_bit()
231 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_IDC_bit()
240 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_IDC_bit()
243 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_IDC_bit()
275 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OOV_bit()
284 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_OOV_bit()
287 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_OOV_bit()
319 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OE_bit()
[all …]
A Dhri_opamp_l10.h232 tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; in hri_opamp_get_OPAMPCTRL_ENABLE_bit()
241 tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; in hri_opamp_write_OPAMPCTRL_ENABLE_bit()
244 ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; in hri_opamp_write_OPAMPCTRL_ENABLE_bit()
272 tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; in hri_opamp_get_OPAMPCTRL_ANAOUT_bit()
281 tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; in hri_opamp_write_OPAMPCTRL_ANAOUT_bit()
284 ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; in hri_opamp_write_OPAMPCTRL_ANAOUT_bit()
312 tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; in hri_opamp_get_OPAMPCTRL_RES2VCC_bit()
321 tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; in hri_opamp_write_OPAMPCTRL_RES2VCC_bit()
324 ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; in hri_opamp_write_OPAMPCTRL_RES2VCC_bit()
352 tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; in hri_opamp_get_OPAMPCTRL_RUNSTDBY_bit()
[all …]
A Dhri_evsys_l10.h656 tmp = ((Evsys *)hw)->USER[index].reg; in hri_evsys_get_USER_CHANNEL_bf()
665 tmp = ((Evsys *)hw)->USER[index].reg; in hri_evsys_write_USER_CHANNEL_bf()
668 ((Evsys *)hw)->USER[index].reg = tmp; in hri_evsys_write_USER_CHANNEL_bf()
689 tmp = ((Evsys *)hw)->USER[index].reg; in hri_evsys_read_USER_CHANNEL_bf()
697 ((Evsys *)hw)->USER[index].reg |= mask; in hri_evsys_set_USER_reg()
705 tmp = ((Evsys *)hw)->USER[index].reg; in hri_evsys_get_USER_reg()
713 ((Evsys *)hw)->USER[index].reg = data; in hri_evsys_write_USER_reg()
720 ((Evsys *)hw)->USER[index].reg &= ~mask; in hri_evsys_clear_USER_reg()
727 ((Evsys *)hw)->USER[index].reg ^= mask; in hri_evsys_toggle_USER_reg()
733 return ((Evsys *)hw)->USER[index].reg; in hri_evsys_read_USER_reg()
[all …]
/bsp/microchip/same54/bsp/hri/
A Dhri_ccl_e54.h204 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_get_SEQCTRL_SEQSEL_bf()
213 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_write_SEQCTRL_SEQSEL_bf()
216 ((Ccl *)hw)->SEQCTRL[index].reg = tmp; in hri_ccl_write_SEQCTRL_SEQSEL_bf()
237 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_read_SEQCTRL_SEQSEL_bf()
253 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_get_SEQCTRL_reg()
294 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_get_LUTCTRL_ENABLE_bit()
303 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_write_LUTCTRL_ENABLE_bit()
306 ((Ccl *)hw)->LUTCTRL[index].reg = tmp; in hri_ccl_write_LUTCTRL_ENABLE_bit()
334 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_get_LUTCTRL_EDGESEL_bit()
343 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_write_LUTCTRL_EDGESEL_bit()
[all …]
A Dhri_gclk_e54.h222 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_GENEN_bit()
231 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_GENEN_bit()
234 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_GENEN_bit()
266 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_IDC_bit()
275 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_IDC_bit()
278 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_IDC_bit()
310 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OOV_bit()
319 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_OOV_bit()
322 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_OOV_bit()
354 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OE_bit()
[all …]
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_ccl_d51.h204 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_get_SEQCTRL_SEQSEL_bf()
213 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_write_SEQCTRL_SEQSEL_bf()
216 ((Ccl *)hw)->SEQCTRL[index].reg = tmp; in hri_ccl_write_SEQCTRL_SEQSEL_bf()
237 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_read_SEQCTRL_SEQSEL_bf()
253 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_get_SEQCTRL_reg()
294 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_get_LUTCTRL_ENABLE_bit()
303 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_write_LUTCTRL_ENABLE_bit()
306 ((Ccl *)hw)->LUTCTRL[index].reg = tmp; in hri_ccl_write_LUTCTRL_ENABLE_bit()
334 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_get_LUTCTRL_EDGESEL_bit()
343 tmp = ((Ccl *)hw)->LUTCTRL[index].reg; in hri_ccl_write_LUTCTRL_EDGESEL_bit()
[all …]
A Dhri_gclk_d51.h222 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_GENEN_bit()
231 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_GENEN_bit()
234 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_GENEN_bit()
266 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_IDC_bit()
275 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_IDC_bit()
278 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_IDC_bit()
310 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OOV_bit()
319 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_OOV_bit()
322 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_OOV_bit()
354 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OE_bit()
[all …]
A Dhri_eic_d51.h740 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_get_CONFIG_FILTEN0_bit()
749 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_write_CONFIG_FILTEN0_bit()
752 ((Eic *)hw)->CONFIG[index].reg = tmp; in hri_eic_write_CONFIG_FILTEN0_bit()
780 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_get_CONFIG_FILTEN1_bit()
789 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_write_CONFIG_FILTEN1_bit()
792 ((Eic *)hw)->CONFIG[index].reg = tmp; in hri_eic_write_CONFIG_FILTEN1_bit()
820 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_get_CONFIG_FILTEN2_bit()
829 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_write_CONFIG_FILTEN2_bit()
832 ((Eic *)hw)->CONFIG[index].reg = tmp; in hri_eic_write_CONFIG_FILTEN2_bit()
860 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_get_CONFIG_FILTEN3_bit()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_ptpc_drv.h82 … ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) in ptpc_set_ns_counter_rollover()
94 ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK; in ptpc_enable_capture_keep()
105 ptr->PTPC[index].CTRL0 &= ~PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK; in ptpc_disable_capture_keep()
117 ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) in ptpc_set_ns_counter_update_type()
130 ptr->PTPC[index].CTRL1 = PTPC_PTPC_CTRL1_SS_INCR_SET(ns_step); in ptpc_set_ns_counter_step()
194 ptr->PTPC[index].TARL = PTPC_PTPC_TARL_TARGET_TIME_LOW_SET(ns); in ptpc_config_compare()
195 ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_COMP_EN_MASK; in ptpc_config_compare()
231 ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK; in ptpc_enable_timer()
242 ptr->PTPC[index].CTRL0 &= ~PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK; in ptpc_disable_timer()
255 ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~(PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK in ptpc_config_capture()
[all …]
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_flexio.c165 base->SHIFTCTL[index] = in FLEXIO_SetShifterConfig()
173 base->TIMCFG[index] = in FLEXIO_SetTimerConfig()
194 uint8_t index = 0; in FLEXIO_RegisterHandleIRQ() local
197 for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) in FLEXIO_RegisterHandleIRQ()
204 s_flexioIsr[index] = isr; in FLEXIO_RegisterHandleIRQ()
223 uint8_t index = 0; in FLEXIO_UnregisterHandleIRQ() local
226 for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) in FLEXIO_UnregisterHandleIRQ()
250 uint8_t index; in FLEXIO_CommonIRQHandler() local
252 for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) in FLEXIO_CommonIRQHandler()
254 if (s_flexioHandle[index]) in FLEXIO_CommonIRQHandler()
[all …]
/bsp/ht32/libraries/ht32_drivers/
A Ddrv_gpio.c22 int index; member
194 if (index->index == -1) in get_pin()
201 return index; in get_pin()
273 GPIO_DirectionConfig(index->gpio, index->pin, GPIO_DIR_IN); in ht32_pin_mode()
275 GPIO_InputConfig(index->gpio, index->pin, ENABLE); in ht32_pin_mode()
279 GPIO_DirectionConfig(index->gpio, index->pin, GPIO_DIR_IN); in ht32_pin_mode()
281 GPIO_InputConfig(index->gpio, index->pin, ENABLE); in ht32_pin_mode()
287 GPIO_InputConfig(index->gpio, index->pin, ENABLE); in ht32_pin_mode()
305 GPIO_ClearOutBits(index->gpio, index->pin); in ht32_pin_write()
309 GPIO_SetOutBits(index->gpio, index->pin); in ht32_pin_write()
[all …]
/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/
A DUnpackImage.py34 index = 0x10
37 … self.img_list.append([int.from_bytes(self.pack_data[index: index + 8], byteorder='little'),
41 …index += int.from_bytes(self.pack_data[index: index + 8], byteorder='little') + 24 # 24 is image …
42 if index % 16 != 0:
43 index += 16 - (index & 0xF) # round to 16-byte align
48 def img_attr(self, index): argument
49 if index < self.image_cnt:
52 return self.img_list[index][0], self.img_list[index][1], self.img_list[index][2]
58 if index >= self.image_cnt:
61 if offset > self.img_list[index][0] or offset + size > self.img_list[index][0]:
[all …]
/bsp/nuvoton/numaker-iot-ma35d1/nuwriter_scripts/
A DUnpackImage.py34 index = 0x10
37 … self.img_list.append([int.from_bytes(self.pack_data[index: index + 8], byteorder='little'),
41 …index += int.from_bytes(self.pack_data[index: index + 8], byteorder='little') + 24 # 24 is image …
42 if index % 16 != 0:
43 index += 16 - (index & 0xF) # round to 16-byte align
48 def img_attr(self, index): argument
49 if index < self.image_cnt:
52 return self.img_list[index][0], self.img_list[index][1], self.img_list[index][2]
58 if index >= self.image_cnt:
61 if offset > self.img_list[index][0] or offset + size > self.img_list[index][0]:
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/
A Dbl808_ef_cfg.c372 if ((index <= 3) || (index == 11)) { in bflb_efuse_write_aes_key()
373 index = ((index == 11) ? 5 : index); in bflb_efuse_write_aes_key()
377 index = index - 4; in bflb_efuse_write_aes_key()
385 if ((index <= 3) || (index == 11)) { in bflb_efuse_read_aes_key()
386 index = ((index == 11) ? 5 : index); in bflb_efuse_read_aes_key()
390 index = index - 4; in bflb_efuse_read_aes_key()
400 if ((index <= 3) || (index == 11)) { in bflb_efuse_lock_aes_key_write()
401 index = ((index == 11) ? 8 : index); in bflb_efuse_lock_aes_key_write()
405 index = index - 4; in bflb_efuse_lock_aes_key_write()
416 index = ((index == 11) ? 4 : index); in bflb_efuse_lock_aes_key_read()
[all …]
/bsp/microchip/same70/bsp/hri/
A Dhri_gpbr_e70b.h58 ((Gpbr *)hw)->SYS_GPBR[index] |= GPBR_SYS_GPBR_GPBR_VALUE(mask); in hri_gpbr_set_SYS_GPBR_GPBR_VALUE_bf()
66 tmp = ((Gpbr *)hw)->SYS_GPBR[index]; in hri_gpbr_get_SYS_GPBR_GPBR_VALUE_bf()
76 tmp = ((Gpbr *)hw)->SYS_GPBR[index]; in hri_gpbr_write_SYS_GPBR_GPBR_VALUE_bf()
79 ((Gpbr *)hw)->SYS_GPBR[index] = tmp; in hri_gpbr_write_SYS_GPBR_GPBR_VALUE_bf()
102 tmp = ((Gpbr *)hw)->SYS_GPBR[index]; in hri_gpbr_read_SYS_GPBR_GPBR_VALUE_bf()
110 ((Gpbr *)hw)->SYS_GPBR[index] |= mask; in hri_gpbr_set_SYS_GPBR_reg()
118 tmp = ((Gpbr *)hw)->SYS_GPBR[index]; in hri_gpbr_get_SYS_GPBR_reg()
126 ((Gpbr *)hw)->SYS_GPBR[index] = data; in hri_gpbr_write_SYS_GPBR_reg()
133 ((Gpbr *)hw)->SYS_GPBR[index] &= ~mask; in hri_gpbr_clear_SYS_GPBR_reg()
140 ((Gpbr *)hw)->SYS_GPBR[index] ^= mask; in hri_gpbr_toggle_SYS_GPBR_reg()
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/
A Dbl616_ef_cfg.c522 if ((index <= 3) || (index == 11)) { in bflb_efuse_write_aes_key()
523 index = ((index == 11) ? 5 : index); in bflb_efuse_write_aes_key()
527 index = index - 4; in bflb_efuse_write_aes_key()
535 if ((index <= 3) || (index == 11)) { in bflb_efuse_read_aes_key()
536 index = ((index == 11) ? 5 : index); in bflb_efuse_read_aes_key()
540 index = index - 4; in bflb_efuse_read_aes_key()
550 if ((index <= 3) || (index == 11)) { in bflb_efuse_lock_aes_key_write()
551 index = ((index == 11) ? 8 : index); in bflb_efuse_lock_aes_key_write()
555 index = index - 4; in bflb_efuse_lock_aes_key_write()
566 index = ((index == 11) ? 4 : index); in bflb_efuse_lock_aes_key_read()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_ptpc_drv.c38 ptpc_disable_timer(ptr, index); in ptpc_init()
46 ptpc_set_ns_counter_step(ptr, index, ss_incr); in ptpc_init()
47 ptpc_enable_timer(ptr, index); in ptpc_init()
75 ptpc_set_second_update(ptr, index, sec); in ptpc_update_timer()
76 ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK; in ptpc_update_timer()
80 void ptpc_init_timer(PTPC_Type *ptr, uint8_t index) in ptpc_init_timer() argument
82 ptpc_set_second_update(ptr, index, 0); in ptpc_init_timer()
83 ptpc_set_ns_update(ptr, index, 0, ptpc_counting_increment); in ptpc_init_timer()
84 ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_INIT_TIMER_MASK; in ptpc_init_timer()
92 ptpc_set_second_update(ptr, index, sec); in ptpc_init_timer_with_initial()
[all …]

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