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Searched refs:kSCG_SysClkDivBy1 (Results 1 – 2 of 2) sorted by relevance

/bsp/rv32m1_vega/ri5cy/board/
A Dclock_config.c74 .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */ in CLOCK_CONFIG_FircSafeConfig()
134 .divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
135 .divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
136 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
241 .divBus = kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
242 .divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
243 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
357 .divExt = kSCG_SysClkDivBy1, /* External Clock Divider: divided by 1 */
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_clock.h440 kSCG_SysClkDivBy1 = 0U, /*!< Divided by 1. */ enumerator

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