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Searched refs:kSCG_SysClkDivBy4 (Results 1 – 2 of 2) sorted by relevance

/bsp/rv32m1_vega/ri5cy/board/
A Dclock_config.c73 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */ in CLOCK_CONFIG_FircSafeConfig()
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_clock.h443 kSCG_SysClkDivBy4 = 3U, /*!< Divided by 4. */ enumerator

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