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Searched refs:kSCG_SysClkDivBy9 (Results 1 – 2 of 2) sorted by relevance

/bsp/rv32m1_vega/ri5cy/board/
A Dclock_config.c240 .divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
355 .divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_clock.h448 kSCG_SysClkDivBy9 = 8U, /*!< Divided by 9. */ enumerator

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