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/bsp/nxp/imx/imxrt/libraries/drivers/vglite/VGLite/
A Dvg_lite_image.c43 uint8_t **memory, in get_buffer_planes() argument
69 memory[0] = (uint8_t *)buffer->memory; in get_buffer_planes()
70 memory[1] = memory[2] = ((uint8_t*)0); in get_buffer_planes()
78 memory[0] = (uint8_t *)buffer->memory; in get_buffer_planes()
80 memory[2] = 0; in get_buffer_planes()
88 memory[0] = (uint8_t *)buffer->memory; in get_buffer_planes()
89 memory[1] = 0; in get_buffer_planes()
90 memory[2] = (uint8_t *)buffer->yuv.v_memory; in get_buffer_planes()
98 memory[0] = (uint8_t *)buffer->memory; in get_buffer_planes()
100 memory[2] = (uint8_t *)buffer->yuv.v_memory; in get_buffer_planes()
[all …]
/bsp/rm48x50/HALCoGen/include/
A Dstd_nhet.h69 HET_MEMORY memory ; member
111 HET_MEMORY memory ; member
153 HET_MEMORY memory ; member
198 HET_MEMORY memory ; member
458 HET_MEMORY memory ; member
499 HET_MEMORY memory ; member
540 HET_MEMORY memory ; member
581 HET_MEMORY memory ; member
622 HET_MEMORY memory ; member
664 HET_MEMORY memory ; member
[all …]
/bsp/stm32/stm32wl55-st-nucleo/board/linker_scripts/
A Dlink.lds3 ** Note: For specific memory allocation, linker and startup files must be customized.
11 _estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
19 ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* Flash memory dedicated to CM4 */
27 /* The startup code into "ROM" Rom type memory */
35 /* The program code and other data into "ROM" Rom type memory */
52 /* Constant data into "ROM" Rom type memory */
107 /* Initialized data sections into "SRAM1" Ram type memory */
120 /* Uninitialized data section into "SRAM1" Ram type memory */
136 /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
147 /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
[all …]
/bsp/stm32/stm32wle5-yizhilian-lm401/board/linker_scripts/
A Dlink.lds3 ** Note: For specific memory allocation, linker and startup files must be customized.
11 _estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
27 /* The startup code into "ROM" Rom type memory */
35 /* The program code and other data into "ROM" Rom type memory */
52 /* Constant data into "ROM" Rom type memory */
107 /* Initialized data sections into "SRAM1" Ram type memory */
120 /* Uninitialized data section into "SRAM1" Ram type memory */
136 /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
147 /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
158 /* User_heap_stack section, used to check that there is enough "SRAM1" Ram type memory left */
/bsp/stm32/stm32wle5-yizhilian-lm402/board/linker_scripts/
A Dlink.lds3 ** Note: For specific memory allocation, linker and startup files must be customized.
11 _estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
27 /* The startup code into "ROM" Rom type memory */
35 /* The program code and other data into "ROM" Rom type memory */
52 /* Constant data into "ROM" Rom type memory */
107 /* Initialized data sections into "SRAM1" Ram type memory */
120 /* Uninitialized data section into "SRAM1" Ram type memory */
136 /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
147 /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
158 /* User_heap_stack section, used to check that there is enough "SRAM1" Ram type memory left */
/bsp/rockchip/rk3500/
A DREADME_ZH.md122 'reserved-memory' linux,cma: addr=10000000 size=800000
123 'reserved-memory' ramoops@110000: addr=110000 size=f0000
139 [I/mm.memblock] System memory:
143 [I/mm.memblock] Reserved memory:
153 [I/mm.memblock] physical memory region [0x0000000000200000-0x0000000000480000] installed to system …
154 [I/mm.memblock] physical memory region [0x00000000048e5000-0x0000000008300000] installed to system …
155 [I/mm.memblock] physical memory region [0x000000000831e000-0x0000000008400000] installed to system …
156 [I/mm.memblock] physical memory region [0x0000000009400000-0x0000000010000000] installed to system …
157 [I/mm.memblock] physical memory region [0x0000000010800000-0x00000000edf00000] installed to system …
158 [I/mm.memblock] physical memory region [0x00000000ee368000-0x00000000eff00000] installed to system …
[all …]
A DREADME.md125 'reserved-memory' linux,cma: addr=10000000 size=800000
126 'reserved-memory' ramoops@110000: addr=110000 size=f0000
142 [I/mm.memblock] System memory:
146 [I/mm.memblock] Reserved memory:
156 [I/mm.memblock] physical memory region [0x0000000000200000-0x0000000000480000] installed to system …
157 [I/mm.memblock] physical memory region [0x00000000048e5000-0x0000000008300000] installed to system …
158 [I/mm.memblock] physical memory region [0x000000000831e000-0x0000000008400000] installed to system …
159 [I/mm.memblock] physical memory region [0x0000000009400000-0x0000000010000000] installed to system …
160 [I/mm.memblock] physical memory region [0x0000000010800000-0x00000000edf00000] installed to system …
161 [I/mm.memblock] physical memory region [0x00000000ee368000-0x00000000eff00000] installed to system …
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/
A Dde_dcsc.c160 void *memory; in de_dcsc_init() local
180 memory = disp_sys_malloc(sizeof(struct __csc2_reg_t)); in de_dcsc_init()
181 if (memory == NULL) { in de_dcsc_init()
189 dcsc_enable_block[screen_id].val = memory; in de_dcsc_init()
194 dcsc_coeff_block[screen_id].val = memory + 0x80; in de_dcsc_init()
199 memory = disp_sys_malloc(sizeof(struct __csc_reg_t)); in de_dcsc_init()
200 if (memory == NULL) { in de_dcsc_init()
208 dcsc_enable_block[screen_id].val = memory; in de_dcsc_init()
213 dcsc_coeff_block[screen_id].val = memory + 0x10; in de_dcsc_init()
218 de_dcsc_set_reg_base(screen_id, memory); in de_dcsc_init()
/bsp/ESP32_C3/idf_port/ld/
A Dmemory.ld8 * This file describes the memory layout (memory blocks) by virtual memory addresses.
26 /* CPU instruction prefetch padding size for memory protection scenario */
32 * physical memory is mapped twice to the vritual address (IRAM and DRAM).
33 * `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory
54 * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
62 * RTC fast memory (executable). Persists over deep sleep.
72 * As C3 only has RTC fast memory, this is not configurable like on other targets
/bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/
A Dlink.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/
A Dlinker.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/
A Dlinker.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-evaluationkit-062S2/board/linker_scripts/
A Dlink.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_CM0P/TOOLCHAIN_ARM/
A Dlinker.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_CM4/TOOLCHAIN_ARM/
A Dlinker.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/
A Dcy8c6xx7_cm4_dual.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
69 ; You can assign sections to this memory region for only one of the cores.
70 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
71 ; Therefore, repurposing this memory region will prevent such middleware from operation.
75 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/
A Dlinker.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-cy8ckit-062-BLE/board/linker_scripts/
A Dlink.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM0P/TOOLCHAIN_ARM/
A Dlinker.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_ARM/
A Dlinker.sct12 ;* input files should be mapped into the output file, and to control the memory
47 ; The defines below describe the location and size of blocks of memory in the target.
48 ; Use these defines to specify the memory regions available for allocation.
50 ; The following defines control RAM and flash memory allocation for the CM4 core.
51 ; You can change the memory allocation by editing RAM and Flash defines.
53 ; Using this memory region for other purposes will lead to unexpected behavior.
75 ; You can assign sections to this memory region for only one of the cores.
76 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
77 ; Therefore, repurposing this memory region will prevent such middleware from operation.
81 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/board/linker_scripts/
A Dlink.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/COMPONENT_CM0P/TOOLCHAIN_ARM/
A Dlinker.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/COMPONENT_CM4/TOOLCHAIN_ARM/
A Dlinker.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/linker_scripts/
A Dlink.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM4 core.
49 ; You can change the memory allocation by editing RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
72 ; You can assign sections to this memory region for only one of the cores.
73 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74 ; Therefore, repurposing this memory region will prevent such middleware from operation.
78 ; The following defines describe device specific memory regions and must not be changed.
[all …]
/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM0P/TOOLCHAIN_ARM/
A Dlinker.sct12 ;* input files should be mapped into the output file, and to control the memory
45 ; The defines below describe the location and size of blocks of memory in the target.
46 ; Use these defines to specify the memory regions available for allocation.
48 ; The following defines control RAM and flash memory allocation for the CM0+ core.
49 ; You can change the memory allocation by editing the RAM and Flash defines.
51 ; Using this memory region for other purposes will lead to unexpected behavior.
66 ; You can assign sections to this memory region for only one of the cores.
67 ; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
68 ; Therefore, repurposing this memory region will prevent such middleware from operation.
72 ; The following defines describe device specific memory regions and must not be changed.
[all …]

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