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Searched refs:mibspiREG1 (Results 1 – 2 of 2) sorted by relevance

/bsp/rm48x50/HALCoGen/source/
A Dsys_startup.c168 mibspiREG1->GCR0 = 0x1U; in _c_int00()
192 while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U) in _c_int00()
/bsp/rm48x50/HALCoGen/include/
A Dreg_mibspi.h98 #define mibspiREG1 ((mibspiBASE_t *)0xFFF7F400U) macro

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