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Searched refs:mibspiREG3 (Results 1 – 2 of 2) sorted by relevance

/bsp/rm48x50/HALCoGen/source/
A Dsys_startup.c173 mibspiREG3->GCR0 = 0x1U; in _c_int00()
196 while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U) in _c_int00()
/bsp/rm48x50/HALCoGen/include/
A Dreg_mibspi.h114 #define mibspiREG3 ((mibspiBASE_t *)0xFFF7F800U) macro

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