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Searched refs:mmio_write_32 (Results 1 – 10 of 10) sorted by relevance

/bsp/cvitek/drivers/libraries/eth/
A Deth_phy_cvitek.c64 mmio_write_32(ETH_PHY_BASE + 0x804, 0x0001); in cv181x_config()
75 mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0500); in cv181x_config()
78 mmio_write_32(ETH_PHY_BASE + 0x040, 0x0c00); in cv181x_config()
81 mmio_write_32(ETH_PHY_BASE + 0x040, 0x0c7e); in cv181x_config()
87 mmio_write_32(ETH_PHY_BASE + 0x800, 0x0906); in cv181x_config()
91 mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0500); in cv181x_config()
128 mmio_write_32(ETH_PHY_BASE + 0x05c, 0x0c10); in cv181x_config()
131 mmio_write_32(ETH_PHY_BASE + 0x068, 0x0003); in cv181x_config()
134 mmio_write_32(ETH_PHY_BASE + 0x054, 0x0000); in cv181x_config()
137 mmio_write_32(ETH_PHY_BASE + 0x07c, 0x1000); in cv181x_config()
[all …]
A Dcvi_eth_phy.c171 mmio_write_32(ETH_PHY_BASE, (val | ETH_PHY_SHUTDOWN) & ETH_PHY_RESET); in eth_config()
173 mmio_write_32(ETH_PHY_BASE, val & ETH_PHY_POWERUP & ETH_PHY_RESET); in eth_config()
175 mmio_write_32(ETH_PHY_BASE, (val & ETH_PHY_POWERUP) | ETH_PHY_RESET_N); in eth_config()
/bsp/cvitek/drivers/
A Ddrv_sdhci.c239 mmio_write_32(BASE + SDIF_ADMA_SA_LOW, dma_addr); in sdhci_prepare_data()
242 mmio_write_32(BASE + SDIF_DMA_ADDRESS, block_cnt); in sdhci_prepare_data()
352 mmio_write_32(BASE + SDIF_ARGUMENT, cmd->arg); in sdhci_send_data_cmd()
460 mmio_write_32(BASE + SDIF_ADMA_SA_LOW, dma_addr); in sdhci_data_irq()
461 mmio_write_32(BASE + SDIF_ADMA_SA_HIGH, 0); in sdhci_data_irq()
487 mmio_write_32(BASE + SDIF_INT_STATUS, mask); in sdhci_transfer_handle_irq()
499 mmio_write_32(BASE + SDIF_ADMA_SA_HIGH, 0); in sdhci_transfer_handle_irq()
654 mmio_write_32(RTCSYS_CTRL, 0x1); in sdhci_pad_setting()
655 mmio_write_32(RTCSYS_CLKMUX, 0x10); in sdhci_pad_setting()
656 mmio_write_32(RTCSYS_CLKBYP, 0xfffffffc); in sdhci_pad_setting()
[all …]
A Ddrv_rtc.c105 mmio_write_32(clk, clk_state); in hal_cvi_rtc_clk_set()
113 mmio_write_32(rtc_base + CVI_RTC_SEC_PULSE_GEN, value); in hal_cvi_rtc_enable_sec_counter()
116 mmio_write_32(rtc_base + CVI_RTC_ANA_CALIB, value); in hal_cvi_rtc_enable_sec_counter()
119 mmio_write_32(rtc_base + CVI_RTC_ALARM_ENABLE, 0x0); in hal_cvi_rtc_enable_sec_counter()
125 mmio_write_32(rtc_base + CVI_RTC_SET_SEC_CNTR_TRIG, 1); in hal_cvi_rtc_set_time()
126 mmio_write_32(rtc_base + RTC_MACRO_RG_SET_T, sec); in hal_cvi_rtc_set_time()
127 mmio_write_32(rtc_base + RTC_MACRO_DA_CLEAR_ALL, 1); in hal_cvi_rtc_set_time()
128 mmio_write_32(rtc_base + RTC_MACRO_DA_SOC_READY, 1); in hal_cvi_rtc_set_time()
129 mmio_write_32(rtc_base + RTC_MACRO_DA_CLEAR_ALL, 0); in hal_cvi_rtc_set_time()
130 mmio_write_32(rtc_base + RTC_MACRO_RG_SET_T, 0); in hal_cvi_rtc_set_time()
[all …]
A Ddrv_por.c37 mmio_write_32(CVI_RTC_REG_BASE + RTC_APB_BUSY_SEL,0x1); in cvi_restart()
40 mmio_write_32(CVI_RTC_CTRL_BASE + RTC_CTRL0_UNLOCKKEY, 0xAB18); in cvi_restart()
42 mmio_write_32(CVI_RTC_REG_BASE + RTC_EN_WARM_RST_REQ, 0x1); in cvi_restart()
48 mmio_write_32( CVI_RTC_CTRL_BASE + RTC_CTRL0,0xFFFF0800 | (0x1 << 4)); in cvi_restart()
A Ddrv_adc.c23 mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value); in cvi_set_saradc_ctrl()
29 mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value); in cvi_reset_saradc_ctrl()
44 mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value); in cvi_set_cyc()
47 mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value); in cvi_set_cyc()
56 mmio_write_32(reg_base + SARADC_TEST_OFFSET, val); in cvi_do_calibration()
60 mmio_write_32(reg_base + SARADC_TRIM_OFFSET, val); in cvi_do_calibration()
A Ddrv_eth.c58 mmio_write_32(ETH_PHY_BASE + 0x804, 0x0001); in cvi_ephy_id_init()
61 mmio_write_32(ETH_PHY_BASE + 0x800, 0x0900); in cvi_ephy_id_init()
64 mmio_write_32(ETH_PHY_BASE + 0x800, 0x0904); in cvi_ephy_id_init()
67 mmio_write_32(ETH_PHY_BASE + 0x008, 0x0043); in cvi_ephy_id_init()
68 mmio_write_32(ETH_PHY_BASE + 0x00c, 0x5649); in cvi_ephy_id_init()
71 mmio_write_32(ETH_PHY_BASE + 0x804, 0x0000); in cvi_ephy_id_init()
A Ddrv_wdt.c27 mmio_write_32(base, CV_TOP_WDT_VAL); in cvi_wdt_top_setting()
31 mmio_write_32(base, val & ~CV_RST_WDT); in cvi_wdt_top_setting()
33 mmio_write_32(base, val | CV_RST_WDT); in cvi_wdt_top_setting()
/bsp/cvitek/c906_little/board/
A Dinterrupt.c35 mmio_write_32((PLIC_ENABLE1 + (mask / 32) * 4), value); in plic_enable_irq()
49 mmio_write_32((PLIC_ENABLE1 + (mask / 32) * 4), value); in plic_disable_irq()
54 mmio_write_32((PLIC_PRIORITY0 + irq * 4), priority); in plic_set_priority()
59 mmio_write_32((PLIC_THRESHOLD), threshold); in plic_set_threshold()
68 mmio_write_32(((uintptr_t) PLIC_PRIORITY0 + i), 0); in plic_init()
73 mmio_write_32((PLIC_PENDING1 + i * 4), 0); in plic_init()
74 mmio_write_32((PLIC_ENABLE1 + i * 4), 0); in plic_init()
193 mmio_write_32(PLIC_CLAIM, irq); in rt_hw_irq_isr()
/bsp/cvitek/drivers/libraries/
A Dmmio.h74 #define mmio_wr32 mmio_write_32
97 static inline void mmio_write_32(uintptr_t addr, uint32_t value) in mmio_write_32() function
137 #define _reg_write(addr, data) mmio_write_32((addr), (data))

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