Home
last modified time | relevance | path

Searched refs:mod_div_adr (Results 1 – 2 of 2) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/
A Dde_clock.c30 .mod_div_adr = 0x0c,
49 .mod_div_adr = 0x0c,
64 .mod_div_adr = 0x0c,
79 reg_val = readl(de_clk_tbl[i].mod_div_adr + de1_base); in de_clk_set_div()
84 writel(reg_val, de_clk_tbl[i].mod_div_adr + de1_base); in de_clk_set_div()
92 reg_val = readl(de_clk_tbl[i].mod_div_adr + de_base); in de_clk_set_div()
97 writel(reg_val, de_clk_tbl[i].mod_div_adr + de_base); in de_clk_set_div()
A Dde_clock.h36 u32 mod_div_adr; member

Completed in 4 milliseconds