| /bsp/nuvoton/libraries/ma35/rtt_port/ |
| A D | drv_epwm_capture.c | 58 uint32_t modid; member
80 …{ .base = EPWM0, .name = "epwm0i0", .irqn = EPWM0P0_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MOD…
81 …{ .base = EPWM0, .name = "epwm0i1", .irqn = EPWM0P0_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MOD…
82 …{ .base = EPWM0, .name = "epwm0i2", .irqn = EPWM0P1_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MOD…
83 …{ .base = EPWM0, .name = "epwm0i3", .irqn = EPWM0P1_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MOD…
84 …{ .base = EPWM0, .name = "epwm0i4", .irqn = EPWM0P2_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MOD…
85 …{ .base = EPWM0, .name = "epwm0i5", .irqn = EPWM0P2_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MOD…
88 …{ .base = EPWM1, .name = "epwm1i0", .irqn = EPWM1P0_IRQn, .rstidx = EPWM1_RST, .modid = EPWM1_MOD…
89 …{ .base = EPWM1, .name = "epwm1i1", .irqn = EPWM1P0_IRQn, .rstidx = EPWM1_RST, .modid = EPWM1_MOD…
90 …{ .base = EPWM1, .name = "epwm1i2", .irqn = EPWM1P1_IRQn, .rstidx = EPWM1_RST, .modid = EPWM1_MOD…
[all …]
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| A D | drv_tpwm.c | 81 uint32_t modid; member
97 { .name = "tpwm0", .base = TIMER0, .rstidx = TMR0_RST, .modid = TMR0_MODULE },
100 { .name = "tpwm1", .base = TIMER1, .rstidx = TMR1_RST, .modid = TMR1_MODULE },
103 { .name = "tpwm2", .base = TIMER2, .rstidx = TMR2_RST, .modid = TMR2_MODULE },
106 { .name = "tpwm3", .base = TIMER3, .rstidx = TMR3_RST, .modid = TMR3_MODULE },
109 { .name = "tpwm4", .base = TIMER4, .rstidx = TMR4_RST, .modid = TMR4_MODULE },
112 { .name = "tpwm5", .base = TIMER5, .rstidx = TMR5_RST, .modid = TMR5_MODULE },
115 { .name = "tpwm6", .base = TIMER6, .rstidx = TMR6_RST, .modid = TMR6_MODULE },
118 { .name = "tpwm7", .base = TIMER7, .rstidx = TMR7_RST, .modid = TMR7_MODULE },
121 { .name = "tpwm8", .base = TIMER8, .rstidx = TMR8_RST, .modid = TMR8_MODULE },
[all …]
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| A D | drv_timer.c | 74 uint32_t modid; member
92 …{ .name = "timer0", .base = TIMER0, .irqn = TMR0_IRQn, .rstidx = TMR0_RST, .modid = TMR0_MODULE …
95 …{ .name = "timer1", .base = TIMER1, .irqn = TMR1_IRQn, .rstidx = TMR1_RST, .modid = TMR1_MODULE …
98 …{ .name = "timer2", .base = TIMER2, .irqn = TMR2_IRQn, .rstidx = TMR2_RST, .modid = TMR2_MODULE …
101 …{ .name = "timer3", .base = TIMER3, .irqn = TMR3_IRQn, .rstidx = TMR3_RST, .modid = TMR3_MODULE …
104 …{ .name = "timer4", .base = TIMER4, .irqn = TMR4_IRQn, .rstidx = TMR4_RST, .modid = TMR4_MODULE …
107 …{ .name = "timer5", .base = TIMER5, .irqn = TMR5_IRQn, .rstidx = TMR5_RST, .modid = TMR5_MODULE …
110 …{ .name = "timer6", .base = TIMER6, .irqn = TMR6_IRQn, .rstidx = TMR6_RST, .modid = TMR6_MODULE …
113 …{ .name = "timer7", .base = TIMER7, .irqn = TMR7_IRQn, .rstidx = TMR7_RST, .modid = TMR7_MODULE …
116 …{ .name = "timer8", .base = TIMER8, .irqn = TMR8_IRQn, .rstidx = TMR8_RST, .modid = TMR8_MODULE …
[all …]
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| A D | drv_ecap.c | 55 uint32_t modid; member
83 …{ .base = ECAP0, .name = "ecap0i0", .irqn = ECAP0_IRQn, .rstidx = ECAP0_RST, .modid = ECAP0_MODUL…
84 …{ .base = ECAP0, .name = "ecap0i1", .irqn = ECAP0_IRQn, .rstidx = ECAP0_RST, .modid = ECAP0_MODUL…
85 …{ .base = ECAP0, .name = "ecap0i2", .irqn = ECAP0_IRQn, .rstidx = ECAP0_RST, .modid = ECAP0_MODUL…
88 …{ .base = ECAP1, .name = "ecap1i0", .irqn = ECAP1_IRQn, .rstidx = ECAP1_RST, .modid = ECAP1_MODUL…
89 …{ .base = ECAP1, .name = "ecap1i1", .irqn = ECAP1_IRQn, .rstidx = ECAP1_RST, .modid = ECAP1_MODUL…
90 …{ .base = ECAP1, .name = "ecap1i2", .irqn = ECAP1_IRQn, .rstidx = ECAP1_RST, .modid = ECAP1_MODUL…
93 …{ .base = ECAP2, .name = "ecap2i0", .irqn = ECAP2_IRQn, .rstidx = ECAP1_RST, .modid = ECAP2_MODUL…
94 …{ .base = ECAP2, .name = "ecap2i1", .irqn = ECAP2_IRQn, .rstidx = ECAP1_RST, .modid = ECAP2_MODUL…
95 …{ .base = ECAP2, .name = "ecap2i2", .irqn = ECAP2_IRQn, .rstidx = ECAP1_RST, .modid = ECAP2_MODUL…
[all …]
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| A D | drv_wdt.c | 76 uint32_t modid; member
96 { .name = "wdt0", .base = WDT0, .irqn = WDT0_IRQn, .modid = WDT0_MODULE },
99 { .name = "wdt1", .base = WDT1, .irqn = WDT1_IRQn, .modid = WDT1_MODULE },
102 { .name = "wdt2", .base = WDT2, .irqn = WDT2_IRQn, .modid = WDT2_MODULE },
157 switch (psNuWdt->modid) in nu_wdt_get_module_clock()
162 ret = CLK_GetModuleClockSource(psNuWdt->modid); in nu_wdt_get_module_clock()
197 LOG_D("[%s] modid=%x src_clk=%d src_hz=%d\n", psNuWdt->name, psNuWdt->modid, src_clk, hz); in nu_wdt_get_working_hz()
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| A D | drv_epwm.c | 49 uint32_t modid; member
57 { .name = "epwm0", .base = EPWM0, .rstidx = EPWM0_RST, .modid = EPWM0_MODULE },
61 { .name = "epwm1", .base = EPWM1, .rstidx = EPWM1_RST, .modid = EPWM1_MODULE },
65 { .name = "epwm2", .base = EPWM2, .rstidx = EPWM2_RST, .modid = EPWM2_MODULE },
197 CLK_EnableModuleClock(nu_epwm_arr[i].modid); in rt_hw_epwm_init()
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| A D | drv_eadc.c | 38 uint32_t modid; member
55 { .name = "eadc0", .base = EADC0, .rstidx = EADC0_RST, .modid = EADC0_MODULE, .chnmask = 0 },
142 CLK_EnableModuleClock(nu_eadc_arr[i].modid); in rt_hw_eadc_init()
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| A D | drv_qei.c | 45 uint32_t modid; member
76 .modid = QEI0_MODULE,
89 .modid = QEI1_MODULE,
102 .modid = QEI2_MODULE,
284 CLK_EnableModuleClock(psNuQei->modid); in rt_hw_qei_init()
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| A D | drv_adc.c | 35 uint32_t modid; member
78 .modid = ADC_MODULE,
128 CLK_SetModuleClock(psNuAdc->modid, 0, CLK_CLKDIV4_ADC(180)); /* Set ADC clock rate to 9MHz */ in _nu_adc_init()
480 CLK_EnableModuleClock(psNuAdc->modid); in _nu_adc_open()
483 SYS_ResetModule(psNuAdc->modid); in _nu_adc_open()
515 CLK_DisableModuleClock(psNuAdc->modid); in _nu_adc_close()
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| A D | drv_scuart.c | 52 uint32_t modid; member
82 .name = "scuart0", .base = SC0, .irqn = SC0_IRQn, .rstidx = SC0_RST, .modid = SC0_MODULE,
87 .name = "scuart1", .base = SC1, .irqn = SC1_IRQn, .rstidx = SC1_RST, .modid = SC1_MODULE,
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| A D | drv_sdio.c | 53 uint32_t modid; member
79 .modid = SDH0_MODULE,
89 .modid = SDH1_MODULE,
603 uint32_t u32ModSrcIdx = CLK_GetModuleClockSource(NuSdh->modid); in nu_sdh_iocfg()
802 CLK_EnableModuleClock(nu_sdh_arr[i].modid); in rt_hw_sdh_init()
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| /bsp/nuvoton/libraries/m460/rtt_port/ |
| A D | drv_bpwm_capture.c | 49 uint32_t modid; member
83 …{ .base = BPWM0, .name = "bpwm0i0", .irqn = BPWM0_IRQn, .rstidx = BPWM0_RST, .modid = BPWM0_MODUL…
84 …{ .base = BPWM0, .name = "bpwm0i1", .irqn = BPWM0_IRQn, .rstidx = BPWM0_RST, .modid = BPWM0_MODUL…
85 …{ .base = BPWM0, .name = "bpwm0i2", .irqn = BPWM0_IRQn, .rstidx = BPWM0_RST, .modid = BPWM0_MODUL…
86 …{ .base = BPWM0, .name = "bpwm0i3", .irqn = BPWM0_IRQn, .rstidx = BPWM0_RST, .modid = BPWM0_MODUL…
87 …{ .base = BPWM0, .name = "bpwm0i4", .irqn = BPWM0_IRQn, .rstidx = BPWM0_RST, .modid = BPWM0_MODUL…
88 …{ .base = BPWM0, .name = "bpwm0i5", .irqn = BPWM0_IRQn, .rstidx = BPWM0_RST, .modid = BPWM0_MODUL…
91 …{ .base = BPWM1, .name = "bpwm1i0", .irqn = BPWM1_IRQn, .rstidx = BPWM1_RST, .modid = BPWM1_MODUL…
92 …{ .base = BPWM1, .name = "bpwm1i1", .irqn = BPWM1_IRQn, .rstidx = BPWM1_RST, .modid = BPWM1_MODUL…
240 CLK_EnableModuleClock(psNuBpwmCap->modid); in nu_bpwmcap_init()
[all …]
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| A D | drv_ecap.c | 60 uint32_t modid; member
89 …{ .base = ECAP0, .name = "ecap0i0", .irqn = ECAP0_IRQn, .rstidx = ECAP0_RST, .modid = ECAP0_MODUL…
90 …{ .base = ECAP0, .name = "ecap0i1", .irqn = ECAP0_IRQn, .rstidx = ECAP0_RST, .modid = ECAP0_MODUL…
91 …{ .base = ECAP0, .name = "ecap0i2", .irqn = ECAP0_IRQn, .rstidx = ECAP0_RST, .modid = ECAP0_MODUL…
94 …{ .base = ECAP1, .name = "ecap1i0", .irqn = ECAP1_IRQn, .rstidx = ECAP1_RST, .modid = ECAP1_MODUL…
95 …{ .base = ECAP1, .name = "ecap1i1", .irqn = ECAP1_IRQn, .rstidx = ECAP1_RST, .modid = ECAP1_MODUL…
96 …{ .base = ECAP1, .name = "ecap1i2", .irqn = ECAP1_IRQn, .rstidx = ECAP1_RST, .modid = ECAP1_MODUL…
99 …{ .base = ECAP2, .name = "ecap2i0", .irqn = ECAP2_IRQn, .rstidx = ECAP1_RST, .modid = ECAP2_MODUL…
100 …{ .base = ECAP2, .name = "ecap2i1", .irqn = ECAP2_IRQn, .rstidx = ECAP1_RST, .modid = ECAP2_MODUL…
101 …{ .base = ECAP2, .name = "ecap2i2", .irqn = ECAP2_IRQn, .rstidx = ECAP1_RST, .modid = ECAP2_MODUL…
[all …]
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| A D | drv_epwm_capture.c | 49 uint32_t modid; member
73 …{ .base = EPWM0, .name = "epwm0i0", .irqn = EPWM0P0_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MOD…
74 …{ .base = EPWM0, .name = "epwm0i1", .irqn = EPWM0P0_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MOD…
75 …{ .base = EPWM0, .name = "epwm0i2", .irqn = EPWM0P1_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MOD…
76 …{ .base = EPWM0, .name = "epwm0i3", .irqn = EPWM0P1_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MOD…
77 …{ .base = EPWM0, .name = "epwm0i4", .irqn = EPWM0P2_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MOD…
78 …{ .base = EPWM0, .name = "epwm0i5", .irqn = EPWM0P2_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MOD…
81 …{ .base = EPWM1, .name = "epwm1i0", .irqn = EPWM1P0_IRQn, .rstidx = EPWM1_RST, .modid = EPWM1_MOD…
82 …{ .base = EPWM1, .name = "epwm1i1", .irqn = EPWM1P0_IRQn, .rstidx = EPWM1_RST, .modid = EPWM1_MOD…
83 …{ .base = EPWM1, .name = "epwm1i2", .irqn = EPWM1P1_IRQn, .rstidx = EPWM1_RST, .modid = EPWM1_MOD…
[all …]
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| A D | drv_tpwm.c | 56 uint32_t modid; member
72 { .name = "tpwm0", .base = TIMER0, .rstidx = TMR0_RST, .modid = TMR0_MODULE },
75 { .name = "tpwm1", .base = TIMER1, .rstidx = TMR1_RST, .modid = TMR1_MODULE },
78 { .name = "tpwm2", .base = TIMER2, .rstidx = TMR2_RST, .modid = TMR2_MODULE },
81 { .name = "tpwm3", .base = TIMER3, .rstidx = TMR3_RST, .modid = TMR3_MODULE },
201 CLK_EnableModuleClock(nu_tpwm_arr[i].modid); in rt_hw_tpwm_init()
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| A D | drv_timer.c | 49 uint32_t modid; member
67 …{ .name = "timer0", .base = TIMER0, .irqn = TMR0_IRQn, .rstidx = TMR0_RST, .modid = TMR0_MODULE …
70 …{ .name = "timer1", .base = TIMER1, .irqn = TMR1_IRQn, .rstidx = TMR1_RST, .modid = TMR1_MODULE …
73 …{ .name = "timer2", .base = TIMER2, .irqn = TMR2_IRQn, .rstidx = TMR2_RST, .modid = TMR2_MODULE …
76 …{ .name = "timer3", .base = TIMER3, .irqn = TMR3_IRQn, .rstidx = TMR3_RST, .modid = TMR3_MODULE …
235 CLK_EnableModuleClock(nu_timer_arr[i].modid); in rt_hw_timer_init()
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| A D | drv_eqei.c | 48 uint32_t modid; member
75 .modid = EQEI0_MODULE,
88 .modid = EQEI1_MODULE,
101 .modid = EQEI2_MODULE,
114 .modid = EQEI3_MODULE,
340 CLK_EnableModuleClock(psNuEqei->modid); in rt_hw_qei_init()
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| A D | drv_scuart.c | 55 uint32_t modid; member
85 .name = "scuart0", .base = SC0, .irqn = SC0_IRQn, .rstidx = SC0_RST, .modid = SC0_MODULE,
90 .name = "scuart1", .base = SC1, .irqn = SC1_IRQn, .rstidx = SC1_RST, .modid = SC1_MODULE,
95 .name = "scuart2", .base = SC2, .irqn = SC2_IRQn, .rstidx = SC2_RST, .modid = SC2_MODULE,
352 CLK_EnableModuleClock(nu_scuart_arr[i].modid); in rt_hw_scuart_init()
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| A D | drv_bpwm.c | 46 uint32_t modid; member
55 { .name = "bpwm0", .base = BPWM0, .rstidx = BPWM0_RST, .modid = BPWM0_MODULE },
59 { .name = "bpwm1", .base = BPWM1, .rstidx = BPWM1_RST, .modid = BPWM1_MODULE },
186 CLK_EnableModuleClock(nu_bpwm_arr[i].modid); in rt_hw_bpwm_init()
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| A D | drv_epwm.c | 46 uint32_t modid; member
54 { .name = "epwm0", .base = EPWM0, .rstidx = EPWM0_RST, .modid = EPWM0_MODULE },
58 { .name = "epwm1", .base = EPWM1, .rstidx = EPWM1_RST, .modid = EPWM1_MODULE },
193 CLK_EnableModuleClock(nu_epwm_arr[i].modid); in rt_hw_epwm_init()
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| A D | drv_sdio.c | 53 uint32_t modid; member
72 .modid = SDH0_MODULE,
82 .modid = SDH1_MODULE,
763 CLK_EnableModuleClock(nu_sdh_arr[i].modid); in rt_hw_sdh_init()
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| /bsp/nuvoton/libraries/m2354/rtt_port/ |
| A D | drv_sdio.c | 53 uint32_t modid; member
72 .modid = SDH0_MODULE,
82 .modid = SDH1_MODULE,
763 CLK_EnableModuleClock(nu_sdh_arr[i].modid); in rt_hw_sdh_init()
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| /bsp/nuvoton/libraries/m480/rtt_port/ |
| A D | drv_sdio.c | 53 uint32_t modid; member
72 .modid = SDH0_MODULE,
82 .modid = SDH1_MODULE,
763 CLK_EnableModuleClock(nu_sdh_arr[i].modid); in rt_hw_sdh_init()
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