| /bsp/avr32/software_framework/drivers/pm/ |
| A D | power_clocks_lib.c | 351 mul = (in_cpu_f * div) / in_osc0_f; in pcl_configure_clocks_uc3c()
353 if (mul > PM_MAX_MUL) in pcl_configure_clocks_uc3c()
369 if (2 * mul > PM_MAX_MUL) in pcl_configure_clocks_uc3c()
371 mul *= 2; in pcl_configure_clocks_uc3c()
385 mul--; in pcl_configure_clocks_uc3c()
392 opt.mul = mul, // MUL=7 in the formula in pcl_configure_clocks_uc3c()
517 if (mul > PM_MAX_MUL) in pcl_configure_clocks_uc3d()
533 if (2 * mul > PM_MAX_MUL) in pcl_configure_clocks_uc3d()
535 mul *= 2; in pcl_configure_clocks_uc3d()
549 mul--; in pcl_configure_clocks_uc3d()
[all …]
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| A D | pm_conf_clocks.c | 70 unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0; in pm_configure_clocks() local
99 mul = (in_cpu_f * div) / in_osc0_f; in pm_configure_clocks()
101 if (mul > PM_MAX_MUL) in pm_configure_clocks()
115 while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ) in pm_configure_clocks()
117 if (2 * mul > PM_MAX_MUL) in pm_configure_clocks()
119 mul *= 2; in pm_configure_clocks()
129 pll_freq = in_osc0_f * mul / (div * (1 << div2_en)); in pm_configure_clocks()
133 mul--; in pm_configure_clocks()
137 , mul // mul in pm_configure_clocks()
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| A D | pm.h | 313 extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int …
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| A D | pm.c | 394 unsigned int mul, in pm_pll_setup() argument
403 u_avr32_pm_pll.PLL.pllmul = mul; in pm_pll_setup()
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| /bsp/at91/at91sam9260/platform/ |
| A D | system_clock.c | 114 unsigned mul, div; in at91_pll_rate() local
117 mul = (reg >> 16) & 0x7ff; in at91_pll_rate()
118 if (div && mul) { in at91_pll_rate()
120 freq *= mul + 1; in at91_pll_rate()
129 unsigned i, div = 0, mul = 0, diff = 1 << 30; in at91_pll_calc() local
163 mul = mul1; in at91_pll_calc()
170 return ret | ((mul - 1) << 16) | div; in at91_pll_calc()
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| /bsp/hpmicro/libraries/hpm_sdk/drivers/src/ |
| A D | hpm_pcfg_drv.c | 77 uint16_t mul = 1; in pcfg_irc24m_config_track() local
86 calculated_freq *= (mul++); in pcfg_irc24m_config_track()
89 | PCFG_TRACK_TARGET_TARGET_SET(mul - 1); in pcfg_irc24m_config_track()
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| /bsp/nxp/lpc/lpc5410x/drivers/ |
| A D | drv_uart.c | 52 baud.mul = baud.div = 0; in lpc_configure()
54 if(!baud.mul) in lpc_configure()
61 LPC_ASYNC_SYSCON->FRGCTRL = ((uint32_t) baud.mul << 8) | 0xFF; in lpc_configure()
315 ub->mul = m; in _UART_CalcMul()
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| /bsp/nxp/lpc/lpc54114-lite/drivers/ |
| A D | drv_gpio.c | 46 int mul = 1; in lpc_pin_get() local
70 hw_pin_num += ((int)(name[i] - '0') * mul); in lpc_pin_get()
71 mul = mul * 10; in lpc_pin_get()
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| /bsp/nxp/lpc/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ |
| A D | system_LPC43xx.c | 745 uint32_t div, mul; in GetPLL1Param() local
749 mul = ((ctrl >> 16) & 0xFF) + 1; in GetPLL1Param()
765 return ((div << 8) | (mul)); in GetPLL1Param()
813 uint32_t mul = 1; in GetClockFreq() local
838 mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */ in GetClockFreq()
851 return ((main_freq * mul) / div); in GetClockFreq()
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| /bsp/xplorer4330/Libraries/Device/NXP/LPC43xx/Source/Templates/ |
| A D | system_LPC43xx.c | 744 uint32_t div, mul; in GetPLL1Param() local
748 mul = ((ctrl >> 16) & 0xFF) + 1; in GetPLL1Param()
764 return ((div << 8) | (mul)); in GetPLL1Param()
812 uint32_t mul = 1; in GetClockFreq() local
837 mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */ in GetClockFreq()
850 return ((main_freq * mul) / div); in GetClockFreq()
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| /bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/ |
| A D | clock.c | 57 uint32_t mul; member
86 .mul = 0,
125 SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul; in _system_clock_source_dfll_set_config_errata_9905()
172 (_system_clock_inst.dfll.mul & 0xffff); in system_clock_source_get_hz()
399 _system_clock_inst.dfll.mul = in system_clock_source_dfll_set_config()
404 _system_clock_inst.dfll.mul = in system_clock_source_dfll_set_config()
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| /bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/ |
| A D | clock.c | 71 uint32_t mul; member
114 .mul = 0,
159 SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul; in _system_clock_source_dfll_set_config_errata_9905()
208 (_system_clock_inst.dfll.mul & 0xffff); in system_clock_source_get_hz()
384 _system_clock_inst.dfll.mul = in system_clock_source_dfll_set_config()
394 _system_clock_inst.dfll.mul = in system_clock_source_dfll_set_config()
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| /bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3/ |
| A D | startup.S | 103 mul t1, t1, t2
109 mul t1, t1, t2
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| A D | vectors.S | 119 mul t1, t1, t0
206 mul t1, t1, t0
369 mul t1, t1, t0
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| /bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/ |
| A D | startup.S | 105 mul t1, t1, t2
111 mul t1, t1, t2
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| A D | vectors.S | 120 mul t1, t1, t0
208 mul t1, t1, t0
373 mul t1, t1, t0
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| /bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/ |
| A D | startup.S | 105 mul t1, t1, t2
111 mul t1, t1, t2
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| /bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/ |
| A D | startup.S | 105 mul t1, t1, t2
111 mul t1, t1, t2
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| A D | vectors.S | 120 mul t1, t1, t0
208 mul t1, t1, t0
374 mul t1, t1, t0
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| /bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/ |
| A D | startup.S | 105 mul t1, t1, t2
111 mul t1, t1, t2
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| A D | vectors.S | 119 mul t1, t1, t0
206 mul t1, t1, t0
369 mul t1, t1, t0
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| /bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/ |
| A D | startup.S | 105 mul t1, t1, t2
111 mul t1, t1, t2
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| /bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/ |
| A D | vectors.S | 73 mul t1, t1, t0
195 mul t2, t2, t3
220 mul t1, t1, t2
282 mul t2, t2, t3
358 mul t2, t2, t3
581 mul t1, t1, t0
741 mul t1, t1, t0
910 mul t1, t1, t0
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| A D | startup.S | 207 mul t1, t1, t2
213 mul t1, t1, t2
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| /bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/ |
| A D | hal_rcc.c | 413 u32 clock, mul, div; in RCC_GetSysClockFreq() local
426 mul = ((RCC->PLLCFGR & (u32)RCC_PLLCFGR_PLL_DN) >> RCC_PLLCFGR_PLL_DN_Pos) + 1; in RCC_GetSysClockFreq()
429 result = clock * mul / div; in RCC_GetSysClockFreq()
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