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Searched refs:op_addr (Results 1 – 25 of 53) sorted by relevance

123

/bsp/synwit/libraries/SWM341_CSL/CMSIS/CoreSupport/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/airm2m/air32f103/libraries/CMSIS/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/tae32f5300/Libraries/CMSIS/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/renesas/ra8m1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/renesas/ra8d1-vision-board/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/renesas/ra6m4-iot/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/renesas/ra6m3-hmi-board/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/renesas/ra4m2-eco/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/renesas/ra8d1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/Core/Include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
333 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
338 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
339 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
368 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/renesas/ra6e2-fpb/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/
A Darmv7m_cachel1.h118 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
123 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
124 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
361 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
366 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
367 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
391 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
396 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
397 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
421 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/renesas/ra4e2-eco/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/
A Darmv7m_cachel1.h119 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
124 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
125 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
368 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
394 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
399 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
400 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
425 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/at32/libraries/CMSIS/include/
A Dcachel1_armv7.h120 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr() local
125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
126 op_addr += __SCB_ICACHE_LINE_SIZE; in SCB_InvalidateICache_by_Addr()
363 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_InvalidateDCache_by_Addr() local
368 …SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateDCache_by_Addr()
369 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_InvalidateDCache_by_Addr()
393 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanDCache_by_Addr() local
398 …SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_CleanDCache_by_Addr()
399 op_addr += __SCB_DCACHE_LINE_SIZE; in SCB_CleanDCache_by_Addr()
423 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; in SCB_CleanInvalidateDCache_by_Addr() local
[all …]
/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/
A Dcore_rv64.h1445 __CBO_INVAL(op_addr); in csi_dcache_invalid_range()
1446 op_addr += linesize; in csi_dcache_invalid_range()
1456 op_addr += linesize; in csi_dcache_invalid_range()
1462 op_addr += linesize; in csi_dcache_invalid_range()
1491 __CBO_CLEAN(op_addr); in csi_dcache_clean_range()
1492 op_addr += linesize; in csi_dcache_clean_range()
1502 op_addr += linesize; in csi_dcache_clean_range()
1508 op_addr += linesize; in csi_dcache_clean_range()
1536 __CBO_FLUSH(op_addr); in csi_dcache_clean_invalid_range()
1537 op_addr += linesize; in csi_dcache_clean_invalid_range()
[all …]
A Dcore_rv32.h1158 unsigned long op_addr = (unsigned long)addr; in csi_dcache_invalid_range() local
1163 __DCACHE_IPA(op_addr); in csi_dcache_invalid_range()
1164 op_addr += linesize; in csi_dcache_invalid_range()
1185 unsigned long op_addr = (unsigned long) addr & CACHE_INV_ADDR_Msk; in csi_dcache_clean_range() local
1190 __DCACHE_CPA(op_addr); in csi_dcache_clean_range()
1191 op_addr += linesize; in csi_dcache_clean_range()
1212 unsigned long op_addr = (unsigned long) addr; in csi_dcache_clean_invalid_range() local
1217 __DCACHE_CIPA(op_addr); in csi_dcache_clean_invalid_range()
1218 op_addr += linesize; in csi_dcache_clean_invalid_range()
/bsp/essemi/es32vf2264/libraries/RV_CORE/Include/
A Dcore_rv32.h1020 uint32_t op_addr = (uint32_t)addr; in csi_dcache_invalid_range() local
1026 __DCACHE_IPA(op_addr); in csi_dcache_invalid_range()
1027 op_addr += linesize; in csi_dcache_invalid_range()
1048 uint32_t op_addr = (uint32_t) addr & CACHE_INV_ADDR_Msk; in csi_dcache_clean_range() local
1054 __DCACHE_CPA(op_addr); in csi_dcache_clean_range()
1055 op_addr += linesize; in csi_dcache_clean_range()
1076 uint32_t op_addr = (uint32_t) addr; in csi_dcache_clean_invalid_range() local
1082 __DCACHE_CIPA(op_addr); in csi_dcache_clean_invalid_range()
1083 op_addr += linesize; in csi_dcache_clean_invalid_range()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/
A Dcore_rv64.h994 uint64_t op_addr = (uint64_t)addr; in csi_dcache_invalid_range() local
1000 __DCACHE_IPA(op_addr); in csi_dcache_invalid_range()
1001 op_addr += linesize; in csi_dcache_invalid_range()
1019 uint64_t op_addr = (uint64_t)addr & CACHE_INV_ADDR_Msk; in csi_dcache_clean_range() local
1025 __DCACHE_CPA(op_addr); in csi_dcache_clean_range()
1026 op_addr += linesize; in csi_dcache_clean_range()
1044 uint64_t op_addr = (uint64_t)addr; in csi_dcache_clean_invalid_range() local
1050 __DCACHE_CIPA(op_addr); in csi_dcache_clean_invalid_range()
1051 op_addr += linesize; in csi_dcache_clean_invalid_range()
A Dcore_rv32.h1205 uint32_t op_addr = (uint32_t)addr; in csi_dcache_invalid_range() local
1211 __DCACHE_IPA(op_addr); in csi_dcache_invalid_range()
1212 op_addr += linesize; in csi_dcache_invalid_range()
1230 uint32_t op_addr = (uint32_t)addr & CACHE_INV_ADDR_Msk; in csi_dcache_clean_range() local
1236 __DCACHE_CPA(op_addr); in csi_dcache_clean_range()
1237 op_addr += linesize; in csi_dcache_clean_range()
1255 uint32_t op_addr = (uint32_t)addr; in csi_dcache_clean_invalid_range() local
1261 __DCACHE_CIPA(op_addr); in csi_dcache_clean_invalid_range()
1262 op_addr += linesize; in csi_dcache_clean_invalid_range()
/bsp/thead-smart/drivers/
A Dcore_rv32.h1121 uint32_t op_addr = (uint32_t)addr; in csi_dcache_invalid_range() local
1127 __DCACHE_IPA(op_addr); in csi_dcache_invalid_range()
1128 op_addr += linesize; in csi_dcache_invalid_range()
1149 uint32_t op_addr = (uint32_t) addr & CACHE_INV_ADDR_Msk; in csi_dcache_clean_range() local
1155 __DCACHE_CPA(op_addr); in csi_dcache_clean_range()
1156 op_addr += linesize; in csi_dcache_clean_range()
1177 uint32_t op_addr = (uint32_t) addr; in csi_dcache_clean_invalid_range() local
1183 __DCACHE_CIPA(op_addr); in csi_dcache_clean_invalid_range()
1184 op_addr += linesize; in csi_dcache_clean_invalid_range()

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