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Searched refs:pReg (Results 1 – 17 of 17) sorted by relevance

/bsp/rockchip/common/rk_hal/lib/hal/src/
A Dhal_uart.c51 UART_EnableDLAB(pReg); in UART_SetBaudRate()
56 UART_DisableDLAB(pReg); in UART_SetBaudRate()
104 pReg->LCR = lcr; in UART_SetLcrReg()
206 return pReg->LSR; in HAL_UART_GetLsr()
218 return pReg->USR; in HAL_UART_GetUsr()
230 return pReg->MSR; in HAL_UART_GetMsr()
322 pReg->IER = 0; in HAL_UART_Reset()
323 pReg->DMASA = 1; in HAL_UART_Reset()
339 pReg = dev->pReg; in HAL_UART_Init()
365 pReg->FCR = in HAL_UART_Init()
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A Dhal_timer.c72 if (pReg == SYS_TIMER) { in HAL_TIMER_Init()
96 pReg->LOAD_COUNT[0] = 0xFFFFFFFFU; in HAL_TIMER_SysTimerInit()
97 pReg->LOAD_COUNT[1] = 0xFFFFFFFFU; in HAL_TIMER_SysTimerInit()
113 if (pReg == SYS_TIMER) { in HAL_TIMER_DeInit()
118 WRITE_REG(pReg->CONTROLREG, 0); in HAL_TIMER_DeInit()
138 if (pReg == SYS_TIMER) { in HAL_TIMER_Start()
159 if (pReg == SYS_TIMER) { in HAL_TIMER_Stop()
178 if (pReg == SYS_TIMER) { in HAL_TIMER_Start_IT()
198 if (pReg == SYS_TIMER) { in HAL_TIMER_Stop_IT()
221 if (pReg == SYS_TIMER) { in HAL_TIMER_SetCount()
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A Dhal_pwm.c45 #define PWM_CNT_REG(pPWM, ch) (pPWM->pReg->CHANNELS[ch].CNT)
108 uint32_t status = READ_REG(pPWM->pReg->INTSTS); in HAL_PWM_IRQHandler()
112 WRITE_REG(pPWM->pReg->INTSTS, status & 0xf); in HAL_PWM_IRQHandler()
260 SET_BIT(pPWM->pReg->INT_EN, PWM_PWR_INT_EN(channel)); in HAL_PWM_SetMatch()
262 SET_BIT(pPWM->pReg->PWRMATCH_CTRL, channel); in HAL_PWM_SetMatch()
305 intEnable = READ_REG(pPWM->pReg->INT_EN); in HAL_PWM_Enable()
308 WRITE_REG(pPWM->pReg->INT_EN, intEnable); in HAL_PWM_Enable()
336 intEnable = READ_REG(pPWM->pReg->INT_EN); in HAL_PWM_Disable()
339 WRITE_REG(pPWM->pReg->INT_EN, intEnable); in HAL_PWM_Disable()
370 pPWM->pReg = pReg; in HAL_PWM_Init()
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A Dhal_dwdma.c166 struct DMA_REG *reg = dw->pReg; in DWDMA_off()
183 struct DMA_REG *reg = dw->pReg; in DWDMA_on()
228 WRITE_REG(dw->pReg->CLEAR.TFR, dwc->mask); in DWC_deinitialize()
231 WRITE_REG(dw->pReg->CLEAR.ERR, dwc->mask); in DWC_deinitialize()
296 return READ_REG(dw->pReg->RAW.BLOCK); in HAL_DWDMA_GetRawBlockStatus()
308 return READ_REG(dw->pReg->RAW.ERR); in HAL_DWDMA_GetRawErrStatus()
320 return READ_REG(dw->pReg->RAW.TFR); in HAL_DWDMA_GetRawXferStatus()
335 struct DMA_REG *reg = dw->pReg; in HAL_DWDMA_Init()
353 dwc->creg = &(dw->pReg->CHAN[i]); in HAL_DWDMA_Init()
459 reg = dw->pReg; in HAL_DWDMA_Start()
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A Dhal_pl330.c1173 struct DMA_REG *reg = pl330->pReg; in PL330_Read_Config()
1377 struct DMA_REG *reg = pl330->pReg; in HAL_PL330_GetRawIrqStatus()
1392 struct DMA_REG *reg = pl330->pReg; in HAL_PL330_ClearIrq()
1411 struct DMA_REG *reg = pl330->pReg; in HAL_PL330_GetPosition()
1478 struct DMA_REG *reg = pl330->pReg; in HAL_PL330_DeInit()
1532 struct DMA_REG *reg = pl330->pReg; in HAL_PL330_Start()
1572 uint32_t intEn = READ_REG(pchan->pl330->pReg->INTEN); in HAL_PL330_Stop()
1576 PL330_Exec_DMAKILL(pchan->pl330->pReg, pchan->chanId, 1); in HAL_PL330_Stop()
1596 struct DMA_REG *reg = pl330->pReg; in HAL_PL330_IrqHandler()
1609 PL330_Exec_DMAKILL(pl330->pReg, 0, 0); in HAL_PL330_IrqHandler()
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/bsp/rockchip/common/rk_hal/lib/hal/inc/
A Dhal_uart.h214 struct UART_REG *pReg; /**< registers base address */ member
250 void HAL_UART_EnableLoopback(struct UART_REG *pReg);
251 void HAL_UART_DisableLoopback(struct UART_REG *pReg);
252 void HAL_UART_EnableAutoFlowControl(struct UART_REG *pReg);
254 uint32_t HAL_UART_GetIrqID(struct UART_REG *pReg);
255 uint32_t HAL_UART_GetLsr(struct UART_REG *pReg);
256 uint32_t HAL_UART_GetUsr(struct UART_REG *pReg);
257 uint32_t HAL_UART_GetMsr(struct UART_REG *pReg);
261 HAL_Status HAL_UART_HandleIrq(struct UART_REG *pReg);
262 void HAL_UART_Reset(struct UART_REG *pReg);
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A Dhal_timer.h43 HAL_Status HAL_TIMER_Stop(struct TIMER_REG *pReg);
44 HAL_Status HAL_TIMER_Start(struct TIMER_REG *pReg);
45 HAL_Status HAL_TIMER_Stop_IT(struct TIMER_REG *pReg);
46 HAL_Status HAL_TIMER_Start_IT(struct TIMER_REG *pReg);
47 HAL_Status HAL_TIMER_SetCount(struct TIMER_REG *pReg, uint64_t usTick);
48 uint64_t HAL_TIMER_GetCount(struct TIMER_REG *pReg);
51 HAL_Status HAL_TIMER_Init(struct TIMER_REG *pReg, eTIMER_MODE mode);
52 HAL_Status HAL_TIMER_SysTimerInit(struct TIMER_REG *pReg);
53 HAL_Status HAL_TIMER_DeInit(struct TIMER_REG *pReg);
54 HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg);
A Dhal_pwm.h43 struct PWM_REG *pReg; member
92 struct PWM_REG *pReg; member
116 HAL_Status HAL_PWM_Init(struct PWM_HANDLE *pPWM, struct PWM_REG *pReg, uint32_t freq);
A Dhal_dwdma.h166 struct DMA_REG *pReg; member
A Dhal_pl330.h192 struct DMA_REG *pReg; member
/bsp/n32/libraries/N32G45x_Firmware_Library/n32g45x_std_periph_driver/src/
A Dn32g45x_tsc.c155 uint32_t i,chn,timeout,*pReg,nPos; in TSC_ConfigInternalResistor() local
185 pReg = (uint32_t *)(&(TSC_Def->RESR0)); in TSC_ConfigInternalResistor()
186 pReg += (i/8); in TSC_ConfigInternalResistor()
188 MODIFY_REG(*pReg,TSC_RESR_CHN_RESIST_MASK<<nPos,res<<nPos); in TSC_ConfigInternalResistor()
209 uint32_t i, chn,timeout,*pReg; in TSC_ConfigThreshold() local
232 pReg = (uint32_t *)(&(TSC_Def->THRHD0)); in TSC_ConfigThreshold()
263 uint32_t i,chn, *pReg; in TSC_GetChannelCfg() local
278 pReg = (uint32_t *)(&(TSC->THRHD0)); in TSC_GetChannelCfg()
279 pReg += i; in TSC_GetChannelCfg()
283 pReg = (uint32_t *)(&(TSC->RESR0)); in TSC_GetChannelCfg()
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/bsp/n32/libraries/N32G4FR_Firmware_Library/n32g4fr_std_periph_driver/src/
A Dn32g4fr_tsc.c155 uint32_t i,chn,timeout,*pReg,nPos; in TSC_ConfigInternalResistor() local
185 pReg = (uint32_t *)(&(TSC_Def->RESR0)); in TSC_ConfigInternalResistor()
186 pReg += (i/8); in TSC_ConfigInternalResistor()
188 MODIFY_REG(*pReg,TSC_RESR_CHN_RESIST_MASK<<nPos,res<<nPos); in TSC_ConfigInternalResistor()
209 uint32_t i, chn,timeout,*pReg; in TSC_ConfigThreshold() local
232 pReg = (uint32_t *)(&(TSC_Def->THRHD0)); in TSC_ConfigThreshold()
263 uint32_t i,chn, *pReg; in TSC_GetChannelCfg() local
278 pReg = (uint32_t *)(&(TSC->THRHD0)); in TSC_GetChannelCfg()
279 pReg += i; in TSC_GetChannelCfg()
283 pReg = (uint32_t *)(&(TSC->RESR0)); in TSC_GetChannelCfg()
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/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_std_periph_driver/src/
A Dn32wb452_tsc.c155 uint32_t i,chn,timeout,*pReg,nPos; in TSC_ConfigInternalResistor() local
185 pReg = (uint32_t *)(&(TSC_Def->RESR0)); in TSC_ConfigInternalResistor()
186 pReg += (i/8); in TSC_ConfigInternalResistor()
188 MODIFY_REG(*pReg,TSC_RESR_CHN_RESIST_MASK<<nPos,res<<nPos); in TSC_ConfigInternalResistor()
209 uint32_t i, chn,timeout,*pReg; in TSC_ConfigThreshold() local
232 pReg = (uint32_t *)(&(TSC_Def->THRHD0)); in TSC_ConfigThreshold()
263 uint32_t i,chn, *pReg; in TSC_GetChannelCfg() local
278 pReg = (uint32_t *)(&(TSC->THRHD0)); in TSC_GetChannelCfg()
279 pReg += i; in TSC_GetChannelCfg()
283 pReg = (uint32_t *)(&(TSC->RESR0)); in TSC_GetChannelCfg()
[all …]
/bsp/hc32l196/Libraries/HC32L196_StdPeriph_Driver/src/
A Dhc32l196_dmac.c406 volatile uint32_t *pReg = (&M0P_DMAC->CONFA0+enCh); in Dma_SetBlockSize() local
408 …*pReg = ((*pReg) & ((uint32_t)~DMA_BC_SEL_Msk)) | ((((uint32_t)u16BlkSize-1)&0x0f)<<DMA_BC_SEL_Pos… in Dma_SetBlockSize()
425 volatile uint32_t *pReg = (&M0P_DMAC->CONFA0+enCh); in Dma_SetTransferCnt() local
427 *pReg = ((*pReg)&((uint32_t)~DMA_TC_SEL_Msk))|(((uint32_t)(u16TrnCnt-1)<<DMA_TC_SEL_Pos)); in Dma_SetTransferCnt()
535 volatile uint32_t *pReg = (&M0P_DMAC->CONFA0+enCh); in Dma_SetTransferWidth() local
537 *pReg = ((*pReg)&((uint32_t)~DMA_TRANSFER_WIDTH_Msk))|((uint32_t)enWidth); in Dma_SetTransferWidth()
/bsp/rockchip/common/drivers/
A Ddrv_uart.c174 HAL_UART_SerialOutChar(uart->dev->pReg, c); in rockchip_uart_putc()
188 ret = HAL_UART_SerialIn(uart->dev->pReg, &c, 1); in rockchip_uart_getc()
304 HAL_UART_SerialOutChar(uart->dev->pReg, *str); in rt_hw_console_output()
339 HAL_UART_EnableAutoFlowControl(dev->pReg); in rockchip_uart_configure()
341 HAL_UART_DisableAutoFlowControl(dev->pReg); in rockchip_uart_configure()
357 hw_base = uart->dev->pReg; in rockchip_uart_control()
400 hw_base = uart->dev->pReg; in rockchip_uart_irq()
448 HAL_UART_Suspend(dev->pReg, &pUartSave); in rockchip_uart_suspend()
465 HAL_UART_Reset(dev->pReg); in rockchip_uart_resume()
466 HAL_UART_Resume(dev->pReg, &pUartSave); in rockchip_uart_resume()
[all …]
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_tim.h1354 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); in LL_TIM_OC_ConfigOutput()
1483 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); in LL_TIM_OC_EnableFast()
1505 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); in LL_TIM_OC_DisableFast()
1528 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); in LL_TIM_OC_IsEnabledFast()
1549 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); in LL_TIM_OC_EnablePreload()
1570 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); in LL_TIM_OC_DisablePreload()
1592 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); in LL_TIM_OC_IsEnabledPreload()
1616 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); in LL_TIM_OC_EnableClear()
1639 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); in LL_TIM_OC_DisableClear()
1665 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); in LL_TIM_OC_IsEnabledClear()
[all …]
/bsp/rockchip/common/rk_hal/lib/bsp/RK2108/
A Dhal_bsp.c11 .pReg = UART2,

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