| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/ |
| A D | ccu_phase.c | 12 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
19 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
20 delay = (reg >> phase->shift); in ccu_phase_get_phase()
21 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
65 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
129 __cspr = hal_spin_lock_irqsave(&phase->common.lock); in ccu_phase_set_phase()
130 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
131 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
132 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
133 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
[all …]
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| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/ |
| A D | bflb_i2c.c | 78 uint32_t phase; in bflb_i2c_set_frequence() local
86 tmp = ((phase / 4) / 0.5); in bflb_i2c_set_frequence()
88 tmp = (phase / 4); in bflb_i2c_set_frequence()
91 regval = (phase - tmp) << I2C_CR_I2C_PRD_S_PH_0_SHIFT; in bflb_i2c_set_frequence()
92 regval |= (phase + tmp) << I2C_CR_I2C_PRD_S_PH_1_SHIFT; in bflb_i2c_set_frequence()
93 regval |= (phase) << I2C_CR_I2C_PRD_S_PH_2_SHIFT; in bflb_i2c_set_frequence()
94 regval |= (phase) << I2C_CR_I2C_PRD_S_PH_3_SHIFT; in bflb_i2c_set_frequence()
99 regval = (phase - tmp) << I2C_CR_I2C_PRD_D_PH_0_SHIFT; in bflb_i2c_set_frequence()
100 regval |= (phase + tmp) << I2C_CR_I2C_PRD_D_PH_1_SHIFT; in bflb_i2c_set_frequence()
101 regval |= (phase + tmp) << I2C_CR_I2C_PRD_D_PH_2_SHIFT; in bflb_i2c_set_frequence()
[all …]
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| /bsp/ti/c28x/libraries/HAL_Drivers/ |
| A D | drv_pwm.c | 133 rt_uint32_t phase = configuration->phase; in drv_pwm_set() local
177 if(phase<180) in drv_pwm_set()
179 epwm->TBPHS.bit.TBPHS = prd * phase/180; in drv_pwm_set()
183 epwm->TBPHS.bit.TBPHS = prd-prd * (phase-180)/180; in drv_pwm_set()
261 static rt_err_t drv_pwm_set_phase(struct EPWM_REGS *epwm, rt_uint32_t phase) in drv_pwm_set_phase() argument
267 if(phase<180) in drv_pwm_set_phase()
269 epwm->TBPHS.bit.TBPHS = epwm->TBPRD * phase/180; in drv_pwm_set_phase()
273 epwm->TBPHS.bit.TBPHS = epwm->TBPRD-epwm->TBPRD * (phase-180)/180; in drv_pwm_set_phase()
345 return drv_pwm_set_phase((struct EPWM_REGS *)(pwm->pwm_regs), configuration->phase); in drv_pwm_control()
573 .phase = 0, in c28x_pwm_init()
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| /bsp/hpmicro/libraries/hpm_sdk/drivers/inc/ |
| A D | hpm_romapi_xpi_def.h | 205 #define SUB_INSTR(phase, pad, op) ((uint32_t)(((uint16_t)(phase) << 10) | ((uint16_t)(pad) << 8) | … argument
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| /bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/ |
| A D | fsl_flexio_spi.c | 182 if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) in FLEXIO_SPI_MasterInit()
206 if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) in FLEXIO_SPI_MasterInit()
286 masterConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; in FLEXIO_SPI_MasterGetDefaultConfig()
329 if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) in FLEXIO_SPI_SlaveInit()
351 if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) in FLEXIO_SPI_SlaveInit()
375 if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) in FLEXIO_SPI_SlaveInit()
407 slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; in FLEXIO_SPI_SlaveGetDefaultConfig()
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| A D | fsl_flexio_spi.h | 119 flexio_spi_clock_phase_t phase; /*!< Clock phase. */ member
132 flexio_spi_clock_phase_t phase; /*!< Clock phase. */ member
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| /bsp/hpmicro/libraries/hpm_sdk/drivers/src/ |
| A D | hpm_qeiv2_drv.c | 120 void qeiv2_config_filter(QEIV2_Type *qeiv2_x, qeiv2_filter_phase_t phase, bool outinv, qeiv2_filter… in qeiv2_config_filter() argument
137 qeiv2_x->FILT_CFG[phase] = in qeiv2_config_filter()
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| /bsp/nxp/lpc/lpc54114-lite/drivers/ |
| A D | drv_spi.c | 72 masterConfig.phase = kSPI_ClockPhaseSecondEdge; in spi_init()
76 masterConfig.phase = kSPI_ClockPhaseFirstEdge; in spi_init()
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| /bsp/apm32/libraries/APM32S10x_Library/APM32S10x_StdPeriphDriver/src/ |
| A D | apm32s10x_spi.c | 77 spiConfig->phase | spiConfig->nss | in SPI_Config()
95 spiConfig->phase = SPI_CLKPHA_1EDGE; in SPI_ConfigStructInit()
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| A D | apm32s10x_usart.c | 150 usart->CTRL2_B.CPHA = clockConfig->phase; in USART_ConfigClock()
166 clockConfig->phase = USART_CLKPHA_1EDGE; in USART_ConfigClockStructInit()
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| /bsp/nxp/imx/imx6ull-smart/drivers/ |
| A D | drv_spi.c | 75 config.channelConfig.phase = kECSPI_ClockPhaseSecondEdge; in imx6ull_ecspi_configure()
79 config.channelConfig.phase = kECSPI_ClockPhaseFirstEdge; in imx6ull_ecspi_configure()
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| /bsp/apm32/libraries/APM32E10x_Library/APM32E10x_StdPeriphDriver/src/ |
| A D | apm32e10x_spi.c | 82 spiConfig->phase | spiConfig->nss | in SPI_Config()
170 spiConfig->phase = SPI_CLKPHA_1EDGE; in SPI_ConfigStructInit()
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| A D | apm32e10x_usart.c | 160 usart->CTRL2_B.CPHA = clockConfig->phase; in USART_ConfigClock()
177 clockConfig->phase = USART_CLKPHA_1EDGE; in USART_ConfigClockStructInit()
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| /bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/ |
| A D | apm32f10x_spi.c | 82 spiConfig->phase | spiConfig->nss | in SPI_Config()
170 spiConfig->phase = SPI_CLKPHA_1EDGE; in SPI_ConfigStructInit()
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| A D | apm32f10x_usart.c | 160 usart->CTRL2_B.CPHA = clockConfig->phase; in USART_ConfigClock()
176 clockConfig->phase = USART_CLKPHA_1EDGE; in USART_ConfigClockStructInit()
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| /bsp/nxp/lpc/lpc55sxx/Libraries/drivers/ |
| A D | drv_spi.c | 128 masterConfig.phase = kSPI_ClockPhaseSecondEdge; in lpc_spi_init()
132 masterConfig.phase = kSPI_ClockPhaseFirstEdge; in lpc_spi_init()
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/usb/host/ |
| A D | ehci-sched.c | 213 ps->phase, ps->phase_uf, ps->period, in bandwidth_dbg()
227 if (qh->ps.phase == NO_FRAME) /* Bandwidth wasn't reserved */ in reserve_release_intr_bandwidth()
552 qh, qh->ps.phase, qh->ps.usecs, qh->ps.c_usecs); in qh_link_periodic()
558 for (i = qh->ps.phase; i < ehci->periodic_size; i += period) { in qh_link_periodic()
633 for (i = qh->ps.phase; i < ehci->periodic_size; i += period) in qh_unlink_periodic()
644 qh, qh->ps.phase, qh->ps.usecs, qh->ps.c_usecs); in qh_unlink_periodic()
868 if (qh->ps.phase != NO_FRAME) { in qh_schedule()
908 qh->ps.phase = (qh->ps.period ? ehci->random_frame & in qh_schedule()
910 qh->ps.bw_phase = qh->ps.phase & (qh->ps.bw_period - 1); in qh_schedule()
1033 stream->ps.phase = NO_FRAME; in iso_stream_alloc()
[all …]
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| /bsp/essemi/es32f0654/drivers/ |
| A D | drv_spi.c | 74 hspi->init.phase = SPI_CPHA_SECOND; in spi_configure()
78 hspi->init.phase = SPI_CPHA_FIRST; in spi_configure()
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| /bsp/ti/c28x/tms320f28379d/board/ |
| A D | Kconfig | 113 bool "Enable phase"
135 the phase for PWM1 module
333 bool "Enable phase"
355 the phase for PWM2 module
553 bool "Enable phase"
575 the phase for PWM3 module
773 bool "Enable phase"
795 the phase for PWM4 module
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| /bsp/essemi/es32f369x/drivers/ |
| A D | drv_spi.c | 75 hspi->init.phase = SPI_CPHA_SECOND; in spi_configure()
79 hspi->init.phase = SPI_CPHA_FIRST; in spi_configure()
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| /bsp/apm32/libraries/APM32F0xx_Library/APM32F0xx_StdPeriphDriver/src/ |
| A D | apm32f0xx_spi.c | 100 spi->CTRL1_B.CPHA = spiConfig->phase; in SPI_Config()
192 spiConfig->phase = SPI_CLKPHA_1EDGE; in SPI_ConfigStructInit()
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| /bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/ |
| A D | apm32f4xx_spi.c | 97 spi->CTRL1_B.CPHA = spiConfig->phase; in SPI_Config()
198 spiConfig->phase = SPI_CLKPHA_1EDGE; in SPI_ConfigStructInit()
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| A D | apm32f4xx_usart.c | 186 usart->CTRL2_B.CPHA = clockConfig->phase; in USART_ConfigClock()
203 clockConfig->phase = USART_CLKPHA_1EDGE; in USART_ConfigClockStructInit()
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| /bsp/apm32/libraries/APM32S10x_Library/APM32S10x_StdPeriphDriver/inc/ |
| A D | apm32s10x_spi.h | 189 SPI_CLKPHA_T phase; member
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| /bsp/microchip/samd51-adafruit-metro-m4/bsp/hal/documentation/ |
| A D | usb_device_async.rst | 34 * On *SetAddress* request sends no data, just goes to status phase
36 no data, just goes to status phase
115 must be called with data length zero to complete control status phase.
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