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Searched refs:phy_addr (Results 1 – 25 of 60) sorted by relevance

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/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/
A Dxemacpsif_physpeed.c195 if(phy_addr == 0) { in phy_setup_emacps()
196 for (phy_addr = 31; phy_addr > 0; phy_addr--) { in phy_setup_emacps()
206 phy_addr)); in phy_setup_emacps()
213 link_speed = get_IEEE_phy_speed(xemacpsp, phy_addr); in phy_setup_emacps()
290 u32_t phy_addr; in detect_phy() local
297 for (phy_addr = 31; phy_addr > 0; phy_addr--) { in detect_phy()
307 phymapemac0[phy_addr] = TRUE; in detect_phy()
309 phymapemac1[phy_addr] = TRUE; in detect_phy()
339 link_speed = get_IEEE_phy_speed(xemacpsp, phy_addr); in phy_setup_emacps()
444 XEmacPs_PhyRead(xemacpsp, phy_addr, in get_phy_speed_ksz9031()
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A Dxadapter.c247 u32_t phy_link_detect(XEmacPs *xemacp, u32_t phy_addr) in phy_link_detect() argument
254 XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status); in phy_link_detect()
255 XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status); in phy_link_detect()
262 static u32_t phy_link_detect(XAxiEthernet *xemacp, u32_t phy_addr) in phy_link_detect() argument
277 static u32_t phy_link_detect(XEmacLite *xemacp, u32_t phy_addr) in phy_link_detect() argument
284 XEmacLite_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status); in phy_link_detect()
294 u32_t phy_autoneg_status(XEmacPs *xemacp, u32_t phy_addr) in phy_autoneg_status() argument
301 XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status); in phy_autoneg_status()
302 XEmacPs_PhyRead(xemacp, phy_addr, IEEE_STATUS_REG_OFFSET, &status); in phy_autoneg_status()
309 static u32_t phy_autoneg_status(XAxiEthernet *xemacp, u32_t phy_addr) in phy_autoneg_status() argument
[all …]
/bsp/cvitek/drivers/libraries/eth/
A Dcvi_eth_phy.c39 return priv->phy_read(phy_addr, reg_addr, data); in eth_phy_read()
46 return priv->phy_write(phy_addr, reg_addr, data); in eth_phy_write()
58 p->phy_addr = phy_addr; in eth_get_phy_device()
220 uint32_t phy_addr = dev->phy_addr; in eth_phy_reset() local
223 ret = eth_phy_read(priv, phy_addr, CVI_MII_BMCR, &data); in eth_phy_reset()
245 ret = eth_phy_read(priv, phy_addr, CVI_MII_BMCR, &data); in eth_phy_reset()
320 uint8_t phy_addr = phy_dev->phy_addr; in genphy_update_link() local
381 uint8_t phy_addr = phy_dev->phy_addr; in genphy_config_advert() local
478 uint8_t phy_addr = phy_dev->phy_addr; in genphy_setup_forced() local
521 uint8_t phy_addr = phy_dev->phy_addr; in genphy_config_aneg() local
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A Dcvi_eth_phy.h55 typedef int32_t (*csi_eth_phy_read_t)(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< R…
56 typedef int32_t (*csi_eth_phy_write_t)(uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< W…
333 uint32_t phy_addr; member
364 int32_t eth_phy_read(eth_phy_priv_t *priv, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);
365 int32_t eth_phy_write(eth_phy_priv_t *priv, uint8_t phy_addr, uint8_t reg_addr, uint16_t data);
A Deth_phy_cvitek.c320 uint8_t phy_addr = dev->phy_addr; in cv181x_parse_status() local
324 ret = eth_phy_read(priv, phy_addr, CVI_MII_BMSR, &mii_reg); in cv181x_parse_status()
/bsp/allwinner/libraries/sunxi-hal/hal/source/g2d_rcq/
A Dg2d_rcq.c28 (__u32 *)&p_rcq_info->phy_addr); in g2d_top_mem_pool_alloc()
35 void *g2d_top_reg_memory_alloc(__u32 size, void *phy_addr, in g2d_top_reg_memory_alloc() argument
41 *(__u32 *)phy_addr = (unsigned long)p_rcq_info->phy_addr + in g2d_top_reg_memory_alloc()
56 *(__u32 *)phy_addr = (unsigned long)NULL; in g2d_top_reg_memory_alloc()
61 *(__u32 *)phy_addr = (unsigned long)NULL; in g2d_top_reg_memory_alloc()
70 (void *)p_rcq_info->phy_addr, in g2d_top_mem_pool_free()
A Dg2d_rcq.h67 u8 *phy_addr; member
77 u8 *phy_addr; /* it is non-null at rcq mode */ member
83 u8 *phy_addr; member
95 void *g2d_top_reg_memory_alloc(__u32 size, void *phy_addr,
A Dg2d_ovl_u.c122 (void *)&(p_ovl_u->reg_info->phy_addr), p_rcq_info); in ovl_u_rcq_setup()
129 p_ovl_u->reg_blks[0].phy_addr = p_ovl_u->reg_info->phy_addr; in ovl_u_rcq_setup()
136 (void *)&(p_ovl_u->reg_info->phy_addr), p_rcq_info); in ovl_u_rcq_setup()
143 p_ovl_u->reg_blks[1].phy_addr = p_ovl_u->reg_info->phy_addr; in ovl_u_rcq_setup()
150 (void *)&(p_ovl_u->reg_info->phy_addr), p_rcq_info); in ovl_u_rcq_setup()
157 p_ovl_u->reg_blks[2].phy_addr = p_ovl_u->reg_info->phy_addr; in ovl_u_rcq_setup()
A Dg2d_driver_i.h52 unsigned long phy_addr; member
114 void *g2d_malloc(__u32 bytes_num, __u32 *phy_addr);
115 void g2d_free(void *virt_addr, void *phy_addr, unsigned int size);
/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/
A Dhpm_dp83867.c34 static void dp83867_write_phy_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data) in dp83867_write_phy_ext() argument
37 …enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(0) | DP83867_REGCR_DEVAD_… in dp83867_write_phy_ext()
40 enet_write_phy(ptr, phy_addr, DP83867_ADDAR, addr); in dp83867_write_phy_ext()
43 …enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(1) | DP83867_REGCR_DEVAD_S… in dp83867_write_phy_ext()
46 enet_write_phy(ptr, phy_addr, DP83867_ADDAR, data); in dp83867_write_phy_ext()
49 static uint16_t dp83867_read_phy_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr) in dp83867_read_phy_ext() argument
52 …enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(0) | DP83867_REGCR_DEVAD_S… in dp83867_read_phy_ext()
55 enet_write_phy(ptr, phy_addr, DP83867_ADDAR, addr); in dp83867_read_phy_ext()
58 …enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(1) | DP83867_REGCR_DEVAD_S… in dp83867_read_phy_ext()
61 return enet_read_phy(ptr, phy_addr, DP83867_ADDAR); in dp83867_read_phy_ext()
/bsp/mini4020/drivers/
A Ddm9161.c67 rt_uint8_t phy_addr; member
169 sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr); in write_phy()
275 static void update_link_speed(unsigned short phy_addr) in update_link_speed() argument
280 if (!mii_link_ok(phy_addr)) in update_link_speed()
286 read_phy(phy_addr,MII_BMSR,&bmsr); in update_link_speed()
287 read_phy(phy_addr,MII_BMCR,&bmcr); in update_link_speed()
294 read_phy(phy_addr, MII_LPA, &lpa); in update_link_speed()
383 dm9161_device.phy_addr = phy_address; in rt_dm9161_init()
472 read_phy(dm9161_device.phy_addr, MII_DSINTR_REG, &dsintr); in rt_dm9161_open()
474 write_phy(dm9161_device.phy_addr, MII_DSINTR_REG, dsintr); in rt_dm9161_open()
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/bsp/at32/libraries/rt_drivers/
A Ddrv_emac.c70 static uint8_t phy_addr = 0xFF; variable
195 if(emac_phy_register_write(phy_addr, PHY_CONTROL_REG, PHY_RESET_BIT) == ERROR) in emac_phy_register_reset()
205 if(emac_phy_register_read(phy_addr, PHY_CONTROL_REG, &data) == ERROR) in emac_phy_register_reset()
231 if(emac_phy_register_read(phy_addr, PHY_STATUS_REG, &data) == ERROR) in emac_speed_config()
252 if(emac_phy_register_read(phy_addr, PHY_STATUS_REG, &data) == ERROR) in emac_speed_config()
381 while(phy_addr == 0xFF) in rt_at32_emac_init()
900 while(phy_addr == 0xFF) in phy_monitor_thread_entry()
910 phy_addr = i; in phy_monitor_thread_entry()
924 LOG_D("Found a phy, address:0x%02X", phy_addr); in phy_monitor_thread_entry()
928 emac_phy_register_write(phy_addr, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK); in phy_monitor_thread_entry()
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/bsp/allwinner/libraries/sunxi-hal/hal/source/gmac/
A Dhal_geth.c119 value = geth_mdio_read(rt_geth_dev.iobase, phy_addr, reg); in geth_phy_read()
128 geth_mdio_write(rt_geth_dev.iobase, phy_addr, reg, data); in geth_phy_write()
496 uint32_t phy_addr = 0x1f; in geth_phy_init() local
510 phy_addr = i; in geth_phy_init()
514 phy_addr = i; in geth_phy_init()
515 if (phy_addr == 0x1f) { in geth_phy_init()
519 phy_val = geth_phy_read((char *)dev, phy_addr, MII_BMCR,NULL); in geth_phy_init()
520 geth_phy_write((char *)dev, phy_addr, MII_BMCR, phy_val | BMCR_RESET); in geth_phy_init()
523 phy_val = geth_phy_read((char *)dev, phy_addr, MII_BMCR,NULL); in geth_phy_init()
527 phy_val = geth_phy_read((char *)dev, phy_addr, MII_BMCR,NULL); in geth_phy_init()
[all …]
A Dhal_geth_utils.c377 uint32_t geth_mdio_read(unsigned long iobase, int phy_addr, u8 reg) in geth_mdio_read() argument
382 value |= (((phy_addr << 12) & (0x0001F000)) | in geth_mdio_read()
393 uint32_t geth_mdio_write(unsigned long iobase, int phy_addr, u8 reg, u16 data) in geth_mdio_write() argument
398 value |= (((phy_addr << 12) & (0x0001F000)) | in geth_mdio_write()
/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/
A Ddisp_waveform.c187 u32 phy_addr = 0; in get_mode_phy_address() local
192 phy_addr = g_waveform_file.p_init_wf; in get_mode_phy_address()
199 phy_addr = g_waveform_file.p_du_wf; in get_mode_phy_address()
206 phy_addr = g_waveform_file.p_gc16_wf; in get_mode_phy_address()
213 phy_addr = g_waveform_file.p_A2_wf; in get_mode_phy_address()
220 phy_addr = g_waveform_file.p_gc16_local_wf; in get_mode_phy_address()
227 phy_addr = 0; in get_mode_phy_address()
232 return phy_addr; in get_mode_phy_address()
244 extern void *disp_malloc(u32 num_bytes, void *phy_addr);
/bsp/nxp/mcx/mcxn/Libraries/drivers/
A Ddrv_eth.c284 uint8_t phy_addr = 0xFF; in phy_monitor_thread_entry() local
287 while(phy_addr == 0xFF) in phy_monitor_thread_entry()
298 phy_addr = i; in phy_monitor_thread_entry()
312 LOG_D("Found a phy, address:0x%02X", phy_addr); in phy_monitor_thread_entry()
316 ENET_MDIOWrite(EXAMPLE_ENET_BASE, phy_addr, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK); in phy_monitor_thread_entry()
318 ENET_MDIOWrite(EXAMPLE_ENET_BASE, phy_addr, PHY_BASIC_CONTROL_REG, PHY_AUTO_NEGOTIATION_MASK); in phy_monitor_thread_entry()
326 ENET_MDIORead(EXAMPLE_ENET_BASE, phy_addr, PHY_BASIC_STATUS_REG, &status); in phy_monitor_thread_entry()
335 ENET_MDIORead(EXAMPLE_ENET_BASE, phy_addr, PHY_Status_REG, &SR); in phy_monitor_thread_entry()
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_esc_drv.c14 hpm_stat_t esc_mdio_read(ESC_Type *ptr, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) in esc_mdio_read() argument
33 ptr->PHY_ADDR = phy_addr; in esc_mdio_read()
66 hpm_stat_t esc_mdio_write(ESC_Type *ptr, uint8_t phy_addr, uint8_t reg_addr, uint16_t data) in esc_mdio_write() argument
86 ptr->PHY_ADDR = phy_addr; in esc_mdio_write()
A Dhpm_tsw_drv.c18 hpm_stat_t tsw_ep_mdio_read(TSW_Type *ptr, uint8_t port, uint32_t phy_addr, uint32_t reg_addr, uint… in tsw_ep_mdio_read() argument
25 … | TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SET(phy_addr) in tsw_ep_mdio_read()
39 hpm_stat_t tsw_ep_mdio_write(TSW_Type *ptr, uint8_t port, uint32_t phy_addr, uint32_t reg_addr, uin… in tsw_ep_mdio_write() argument
43 … | TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SET(phy_addr) in tsw_ep_mdio_write()
/bsp/apm32/libraries/Drivers/
A Ddrv_eth.c42 static uint8_t phy_addr = 0xFF; variable
377 ETH_Config(&ETH_InitStructure, phy_addr); in rt_apm32_eth_init()
611 uint16_t status = ETH_ReadPHYRegister(phy_addr, PHY_BSR); in phy_linkchange()
621 SR = ETH_ReadPHYRegister(phy_addr, PHY_Status_REG); in phy_linkchange()
683 while(phy_addr == 0xFF) in phy_monitor_thread_entry()
693 phy_addr = i; in phy_monitor_thread_entry()
707 LOG_D("Found a phy, address:0x%02X", phy_addr); in phy_monitor_thread_entry()
711 ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_RESET); in phy_monitor_thread_entry()
713 ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_AUTONEGOTIATION); in phy_monitor_thread_entry()
/bsp/ck802/libraries/include/
A Ddrv_eth_phy.h49 typedef int32_t (*csi_eth_phy_read_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< R…
50 typedef int32_t (*csi_eth_phy_write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< W…
/bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/
A Deth_phy.h49 typedef int32_t (*csi_eth_phy_read_t)(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< R…
50 typedef int32_t (*csi_eth_phy_write_t)(uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< W…
/bsp/cvitek/drivers/
A Ddrv_eth.c133 static int32_t fn_phy_read(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) in fn_phy_read() argument
135 return dw_eth_mac_phy_read(g_mac_handle, phy_addr, reg_addr, data); in fn_phy_read()
138 static int32_t fn_phy_write(uint8_t phy_addr, uint8_t reg_addr, uint16_t data) in fn_phy_write() argument
140 return dw_eth_mac_phy_write(g_mac_handle, phy_addr, reg_addr, data); in fn_phy_write()
/bsp/ck802/libraries/common/eth/
A Dethernet_enc28j60.c69 static uint32_t enc28j60PhyWrite(uint8_t phy_addr, uint8_t reg_addr, uint16_t data);
70 static uint32_t enc28j60Phyregread(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);
379 static uint32_t enc28j60PhyWrite(uint8_t phy_addr, uint8_t reg_addr, uint16_t data) in enc28j60PhyWrite() argument
384 enc28j60Write(MIREGADR, phy_addr); in enc28j60PhyWrite()
409 static uint32_t enc28j60Phyregread(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) in enc28j60Phyregread() argument
416 enc28j60Write(MIREGADR, phy_addr); in enc28j60Phyregread()
1206 int32_t csi_eth_mac_phy_read(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t reg_addr, uint16_t … in csi_eth_mac_phy_read() argument
1215 int32_t csi_eth_mac_phy_write(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t reg_addr, uint16_t… in csi_eth_mac_phy_write() argument
/bsp/allwinner/libraries/sunxi-hal/hal/test/disp2/
A Ddisp_mem.c90 uintptr_t phy_addr; in disp_mem_request() local
98 g_disp_mm[sel].info_base = disp_malloc(size, (void *)&phy_addr); in disp_mem_request()
100 g_disp_mm[sel].mem_start = phy_addr; in disp_mem_request()
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_tsw_drv.h163 hpm_stat_t tsw_ep_mdio_read(TSW_Type *ptr, uint8_t port, uint32_t phy_addr, uint32_t reg_addr, uint…
175 hpm_stat_t tsw_ep_mdio_write(TSW_Type *ptr, uint8_t port, uint32_t phy_addr, uint32_t reg_addr, uin…

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