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Searched refs:phy_clk_gating (Results 1 – 2 of 2) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/
A Dde_dsi_type_28.h33 u32 phy_clk_gating:1; member
A Dde_dsi_28.c837 dsi_dev[sel]->dsi_ctl1.bits.phy_clk_gating = 1; in dsi_dphy_cfg()
855 dsi_dev[sel]->dsi_ctl1.bits.phy_clk_gating = 0; in dsi_io_close()

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