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Searched refs:pll_audio_ctrl (Results 1 – 2 of 2) sorted by relevance

/bsp/allwinner_tina/drivers/
A Ddrv_clock.c37 reg = CCU->pll_audio_ctrl; in audio_get_pll_clk()
251 CCU->pll_audio_ctrl &= ~(0x1 << 31); in audio_set_pll_clk()
272 CCU->pll_audio_ctrl &= ~(0x1 << 31); in audio_set_pll_clk()
276 CCU->pll_audio_ctrl = (0x1 << 31) | (0x0 << 24) | (n << 8) | m; in audio_set_pll_clk()
278 if (wait_pll_stable((rt_uint32_t)(&CCU->pll_audio_ctrl))) in audio_set_pll_clk()
A Ddrv_clock.h143 volatile rt_uint32_t pll_audio_ctrl; /* 0x008 */ member

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