Searched refs:pll_div2 (Results 1 – 4 of 4) sorted by relevance
| /bsp/dm365/platform/ |
| A D | dm365.c | 228 unsigned long pll_div2, pll_div4, pll_div5, in davinci_clk_init() local
284 pll_div2 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV2) & in davinci_clk_init()
291 armrate = pll_rate / pll_div2; /* 594/2 = 297MHz */ in davinci_clk_init()
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| /bsp/avr32/software_framework/drivers/pm/ |
| A D | power_clocks_lib.c | 393 …opt.pll_div2 = div2_en, // pll_div2 Divide the PLL output frequency by 2 (this settings doe… in pcl_configure_clocks_uc3c()
557 …opt.pll_div2 = div2_en, // pll_div2 Divide the PLL output frequency by 2 (this settings doe… in pcl_configure_clocks_uc3d()
678 ….pll_div2 = 1, // pll_div2 Divide the PLL output frequency by 2 (this settings does not cha… in pcl_configure_usb_clock()
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| A D | pm.h | 324 …avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pl…
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| A D | pm.c | 413 unsigned int pll_div2, in pm_pll_set_option() argument
417 u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2); in pm_pll_set_option()
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