Searched refs:pll_div7 (Results 1 – 1 of 1) sorted by relevance

/bsp/dm365/platform/
A D	dm365.c	229 pll_div6, pll_div7, pll_div8; in davinci_clk_init() local 256 pll_div7 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV7) & in davinci_clk_init() 266 ddrrate = pll_rate / pll_div7; /* 486/2 = 243MHz */ in davinci_clk_init()

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