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Searched refs:pll_periph_ctrl (Results 1 – 2 of 2) sorted by relevance

/bsp/allwinner_tina/drivers/
A Ddrv_clock.c121 reg = CCU->pll_periph_ctrl; in periph_get_pll_clk()
397 CCU->pll_periph_ctrl &= ~(0x1 << 31); in periph_set_pll_clk()
401 CCU->pll_periph_ctrl = (0x1 << 31) | (0x1 << 18) | (n << 8) | (k << 4) || (0x1); in periph_set_pll_clk()
402 if (wait_pll_stable((rt_uint32_t)(&CCU->pll_periph_ctrl))) in periph_set_pll_clk()
A Ddrv_clock.h151 volatile rt_uint32_t pll_periph_ctrl; /* 0x028 */ member

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