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Searched refs:pll_ve_ctrl (Results 1 – 2 of 2) sorted by relevance

/bsp/allwinner_tina/drivers/
A Ddrv_clock.c78 reg = CCU->pll_ve_ctrl; in ve_get_pll_clk()
340 CCU->pll_ve_ctrl &= ~(0x1 << 31); in ve_set_pll_clk()
362 CCU->pll_ve_ctrl &= ~(0x1 << 31); in ve_set_pll_clk()
366 CCU->pll_ve_ctrl = (0x1 << 31) | (0x1 << 24) | (n << 8) | m; in ve_set_pll_clk()
367 if (wait_pll_stable((rt_uint32_t)(&CCU->pll_ve_ctrl))) in ve_set_pll_clk()
A Ddrv_clock.h147 volatile rt_uint32_t pll_ve_ctrl; /* 0x018 */ member

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