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Searched refs:pll_video_ctrl (Results 1 – 2 of 2) sorted by relevance

/bsp/allwinner_tina/drivers/
A Ddrv_clock.c53 reg = CCU->pll_video_ctrl; in video_get_pll_clk()
295 CCU->pll_video_ctrl &= ~(0x1 << 31); in video_set_pll_clk()
317 CCU->pll_video_ctrl &= ~(0x1 << 31); in video_set_pll_clk()
321 CCU->pll_video_ctrl = (0x1 << 31) | (0x0 << 30) | (0x1 << 24) | (n << 8) | m; in video_set_pll_clk()
323 if (wait_pll_stable((rt_uint32_t)(&CCU->pll_video_ctrl))) in video_set_pll_clk()
A Ddrv_clock.h145 volatile rt_uint32_t pll_video_ctrl; /* 0x010 */ member

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