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Searched refs:pllmul (Results 1 – 4 of 4) sorted by relevance

/bsp/n32g452xx/Libraries/rt_drivers/
A Ddrv_clk.c123 uint32_t pllmul; in SetSysClockToPLL() local
164 pllmul = RCC_PLL_MUL_6; in SetSysClockToPLL()
170 pllmul = RCC_PLL_MUL_9; in SetSysClockToPLL()
176 pllmul = RCC_PLL_MUL_12; in SetSysClockToPLL()
182 pllmul = RCC_PLL_MUL_14; in SetSysClockToPLL()
188 pllmul = RCC_PLL_MUL_18; in SetSysClockToPLL()
194 pllmul = RCC_PLL_MUL_24; in SetSysClockToPLL()
200 pllmul = RCC_PLL_MUL_32; in SetSysClockToPLL()
208 pllmul = RCC_PLL_MUL_18; in SetSysClockToPLL()
228 RCC_ConfigPll(pllsrc, pllmul); in SetSysClockToPLL()
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Source/Templates/
A Dsystem_stm32l1xx.c212 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; in SystemCoreClockUpdate() local
231 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
233 pllmul = PLLMulTable[(pllmul >> 18)]; in SystemCoreClockUpdate()
241 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
246 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
/bsp/mm32/mm32f3270-100ask-pitaya/board/
A Dboard.c66 uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; in update_systemclock() local
107 pllmul = (RCC->PLLCFGR>>16)&0x7F; // PLL的倍频系数: PLLCFGR[22:16] in update_systemclock()
108 sysclockfreq = pllclk * (pllmul+1) / (prediv+1); in update_systemclock()
/bsp/avr32/software_framework/drivers/pm/
A Dpm.c403 u_avr32_pm_pll.PLL.pllmul = mul; in pm_pll_setup()

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