| /bsp/hpmicro/libraries/hpm_sdk/drivers/inc/ |
| A D | hpm_ppi_drv.h | 191 …ic inline void ppi_config_cs_pin_polarity(PPI_Type *ppi, uint8_t index, ppi_cs_idle_polarity_t pol) in ppi_config_cs_pin_polarity() argument
194 …ppi->PAD_CFG = (ppi->PAD_CFG & ~(((1u << PPI_PAD_CFG_CS_IDLE_ST_SHIFT) << index))) | (((pol << PPI… in ppi_config_cs_pin_polarity()
204 …c inline void ppi_config_dm_pin_polarity(PPI_Type *ppi, uint8_t index, ppi_dm_valid_polarity_t pol) in ppi_config_dm_pin_polarity() argument
208 …x].CFG2 = (ppi->CS[index].CFG2 & ~PPI_CS_CFG2_DM_POLARITY_MASK) | PPI_CS_CFG2_DM_POLARITY_SET(pol); in ppi_config_dm_pin_polarity()
211 if (pol == ppi_dm_valid_pol_high) { in ppi_config_dm_pin_polarity()
228 …tic inline void ppi_config_ctrl_pin_polarity(PPI_Type *ppi, uint8_t index, ppi_ctrl_polarity_t pol) in ppi_config_ctrl_pin_polarity() argument
231 …ppi->PAD_CFG = (ppi->PAD_CFG & ~(((1u << PPI_PAD_CFG_CTRL_PAD_POL_SHIFT) << index))) | (((pol << P… in ppi_config_ctrl_pin_polarity()
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| /bsp/cvitek/drivers/ |
| A D | drv_gpio.c | 68 rt_uint32_t pol; in dwapb_toggle_trigger() local
72 pol = dwapb_read32(base_addr + GPIO_INT_POLARITY); in dwapb_toggle_trigger()
77 pol &= ~BIT(bit); in dwapb_toggle_trigger()
79 pol |= BIT(bit); in dwapb_toggle_trigger()
81 dwapb_write32(base_addr + GPIO_INT_POLARITY, pol); in dwapb_toggle_trigger()
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| /bsp/maxim/libraries/MAX32660PeriphDriver/Include/ |
| A D | tmr.h | 110 unsigned pol; /// Polarity (0 or 1) member
117 unsigned pol; /// PWM polarity (0 or 1) member
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| A D | gpio.h | 231 int GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode, gpio_int_pol_t pol);
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| A D | uart.h | 139 uart_flow_pol_t pol; /** Configure hardware flow control */ member
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| /bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/ |
| A D | hal_tim.c | 1539 void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol) in TIM_SetIC1Plority() argument
1541 (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC1P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC1P); in TIM_SetIC1Plority()
1553 void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol) in TIM_SetIC2Plority() argument
1555 (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC2P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC2P); in TIM_SetIC2Plority()
1567 void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol) in TIM_SetIC3Plority() argument
1569 (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC3P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC3P); in TIM_SetIC3Plority()
1581 void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol) in TIM_SetIC4Plority() argument
1583 (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC4P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC4P); in TIM_SetIC4Plority()
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| /bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/drv/ |
| A D | pmu.h | 112 …andle_t handle, uint32_t wakeup_num, pmu_wakeup_type_e type, pmu_wakeup_pol_e pol, uint8_t enable);
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| /bsp/maxim/libraries/MAX32660PeriphDriver/Source/ |
| A D | tmr.c | 114 ((cfg->pol << MXC_F_TMR_CN_TPOL_POS) & MXC_F_TMR_CN_TPOL); in TMR_Config()
131 MXC_S_TMR_CN_TMODE_PWM | ((cfg->pol << MXC_F_TMR_CN_TPOL_POS) & MXC_F_TMR_CN_TPOL); in TMR_PWMConfig()
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| A D | spimss.c | 79 unsigned int pol, pha; // Polarity and phase of the clock (SPI mode) in SPIMSS_Init() local
106 pol = mode >> 1; // Get the polarity out of the mode input value in SPIMSS_Init()
109 …spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_CTRL_CLKPOL)) | (pol << MXC_F_SPIMSS_CTRL_CLKPOL_POS); //… in SPIMSS_Init()
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| A D | gpio.c | 203 int GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode, gpio_int_pol_t pol) in GPIO_IntConfig() argument
218 switch (pol) { in GPIO_IntConfig()
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| A D | tmr_utils.c | 81 cfg.pol = 0; in TMR_TO_Start()
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| A D | uart.c | 125 …uart->ctrl = (MXC_F_UART_CTRL_ENABLE | cfg->parity | cfg->size | cfg->stop | cfg->flow | cfg->pol); in UART_Init()
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| /bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Inc/ |
| A D | hal_tim.h | 711 void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
712 void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
713 void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
714 void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
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| /bsp/rockchip/common/rk_hal/lib/hal/inc/ |
| A D | hal_pwm.h | 65 bool pol; member
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| /bsp/rockchip/common/rk_hal/lib/hal/src/ |
| A D | hal_pwm.c | 119 pPWM->result[i].pol = status & (1 << (i + 8)); in HAL_PWM_IRQHandler()
120 if (pPWM->result[i].pol) { in HAL_PWM_IRQHandler()
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| /bsp/maxim/libraries/HAL_Drivers/ |
| A D | drv_uart.c | 137 mcu_cfg.pol = UART_FLOW_POL_EN; in mcu_configure()
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/ |
| A D | de_lcd.h | 153 s32 tcon_set_fsync_pol(u32 sel, u32 pol);
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| A D | de_lcd.c | 2004 s32 tcon_set_fsync_pol(u32 sel, u32 pol) in tcon_set_fsync_pol() argument
2006 if (pol) { in tcon_set_fsync_pol()
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| /bsp/nv32f100x/lib/inc/ |
| A D | etm.h | 245 uint8_t pol; /*!< channels polarity */ member
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| /bsp/nv32f100x/lib/src/ |
| A D | etm.c | 863 pETM->POL = pConfig->pol; in ETM_Init()
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