| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/ |
| A D | clk-fixed-factor.c | 29 unsigned long *prate) in clk_factor_round_rate() argument
38 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); in clk_factor_round_rate()
41 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
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| A D | clk-divider.c | 465 unsigned long rate, unsigned long *prate, in divider_round_rate_parent() argument
471 div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags); in divider_round_rate_parent()
473 return DIV_ROUND_UP_ULL((u64) * prate, div); in divider_round_rate_parent()
477 unsigned long rate, unsigned long *prate, in divider_ro_round_rate_parent() argument
493 *prate = clk_hw_round_rate(parent, rate * div); in divider_ro_round_rate_parent()
496 return DIV_ROUND_UP_ULL((u64) * prate, div); in divider_ro_round_rate_parent()
500 unsigned long *prate) in clk_divider_round_rate() argument
512 return divider_ro_round_rate(hw, rate, prate, divider->table, in clk_divider_round_rate()
517 return divider_round_rate(hw, rate, prate, divider->table, in clk_divider_round_rate()
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| A D | ccu_gate.c | 96 unsigned long *prate) in ccu_gate_round_rate() argument
114 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); in ccu_gate_round_rate()
117 return *prate / div; in ccu_gate_round_rate()
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| A D | clk.h | 96 hal_clk_status_t clk_recalc_rate(struct clk *clk, u32 *prate);
111 hal_clk_status_t clk_round_rate(struct clk *clk, u32 rate, u32 *prate);
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| A D | ccu.h | 510 unsigned long rate, unsigned long *prate,
514 unsigned long rate, unsigned long *prate,
778 unsigned long *prate, in divider_round_rate() argument
783 rate, prate, table, width, flags); in divider_round_rate()
787 unsigned long *prate, in divider_ro_round_rate() argument
793 rate, prate, table, width, flags, in divider_ro_round_rate()
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| /bsp/rockchip/rk3500/driver/clk/ |
| A D | clk-rk3588.c | 1191 prate = priv->cpll_hz; in rk3588_top_get_clk()
1193 prate = priv->gpll_hz; in rk3588_top_get_clk()
1202 prate = priv->cpll_hz; in rk3588_top_get_clk()
1571 prate = OSC_HZ; in rk3588_adc_get_clk()
1582 prate = OSC_HZ; in rk3588_adc_get_clk()
1584 prate = 100 * MHz; in rk3588_adc_get_clk()
1670 prate = OSC_HZ; in rk3588_mmc_get_clk()
1682 prate = OSC_HZ; in rk3588_mmc_get_clk()
1704 prate = OSC_HZ; in rk3588_mmc_get_clk()
1712 prate = 702 * MHz; in rk3588_mmc_get_clk()
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| A D | clk-rk3568.c | 2174 rt_uint32_t div, sel, con, prate; in adc_get_clk() local
2186 prate = OSC_HZ; in adc_get_clk()
2190 prate = 100 * MHZ; in adc_get_clk()
2192 return DIV_TO_RATE(prate, div); in adc_get_clk()
2196 prate = adc_get_clk(priv, CLK_TSADC_TSEN); in adc_get_clk()
2197 return DIV_TO_RATE(prate, div); in adc_get_clk()
2207 rt_ubase_t prate = 0; in adc_set_clk() local
2232 prate = adc_get_clk(priv, CLK_TSADC_TSEN); in adc_set_clk()
2233 src_clk_div = RT_DIV_ROUND_UP(prate, rate); in adc_set_clk()
4606 rt_ubase_t *prate) in rk3568_clk_round_rate() argument
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| A D | clk-pll-rk3568.c | 352 rt_size_t rate_count, rt_ubase_t drate, rt_ubase_t *prate) in rk_clk_pll_round_rate() argument
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| A D | clk-pll-rk3588.c | 676 rt_size_t rate_count, rt_ubase_t drate, rt_ubase_t *prate) in rk_clk_pll_round_rate() argument
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/ |
| A D | clk.c | 50 static hal_clk_status_t sunxi_clk_round_rate(hal_clk_id_t clk, u32 rate, u32 *prate);
412 hal_clk_status_t sunxi_clk_round_rate(hal_clk_id_t clk, u32 rate, u32 *prate) in sunxi_clk_round_rate() argument
434 (*prate) = pclk->clk_rate; in sunxi_clk_round_rate()
446 *prate = round_rate; in sunxi_clk_round_rate()
459 *prate = round_rate; in sunxi_clk_round_rate()
788 hal_clk_status_t clk_round_rate(hal_clk_id_t clk, u32 rate, u32 *prate) in clk_round_rate() argument
790 return sunxi_clk_round_rate(clk, rate, prate); in clk_round_rate()
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| A D | clk_periph.c | 407 u32 sunxi_clk_periph_round_rate(clk_periph_pt clk, u32 rate, u32 prate) in sunxi_clk_periph_round_rate() argument
420 round_rate = (prate + rate / 2 - 1); in sunxi_clk_periph_round_rate()
430 return prate; in sunxi_clk_periph_round_rate()
433 round_rate = prate; in sunxi_clk_periph_round_rate()
475 CCMU_DBG("parent rate %dHZ, target rate %dHZ, round rate %dHZ\n", prate, rate, round_rate); in sunxi_clk_periph_round_rate()
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| A D | clk.h | 219 hal_clk_status_t clk_recalc_rate(hal_clk_id_t clk, u32 *prate);
234 hal_clk_status_t clk_round_rate(hal_clk_id_t clk, u32 rate, u32 *prate);
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| A D | clk_periph.h | 225 u32 sunxi_clk_periph_round_rate(clk_periph_pt clk, u32 rate, u32 prate);
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