Searched refs:prcm_base (Results 1 – 2 of 2) sorted by relevance
50 unsigned long prcm_base; in timer_clk_init() local52 prcm_base = AM33XX_PRCM_REGS; in timer_clk_init()55 CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) |= 0x2; in timer_clk_init()58 while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8))) in timer_clk_init()62 CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL); in timer_clk_init()64 CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3; in timer_clk_init()70 CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE; in timer_clk_init()73 while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) != in timer_clk_init()80 while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) != in timer_clk_init()153 unsigned long prcm_base = AM33XX_PRCM_REGS; in rt_hw_cpu_reset() local[all …]
231 unsigned long prcm_base; in poweron_per_domain() local234 prcm_base = AM33XX_PRCM_REGS; in poweron_per_domain()245 PRM_PER_PWRSTCTRL_REG(prcm_base) |= 0x3; in poweron_per_domain()258 unsigned long prcm_base; in start_uart_clk() local260 prcm_base = AM33XX_PRCM_REGS; in start_uart_clk()272 CM_PER_UART1_CLKCTRL_REG(prcm_base) |= 0x2; in start_uart_clk()279 CM_PER_UART2_CLKCTRL_REG(prcm_base) |= 0x2; in start_uart_clk()286 CM_PER_UART3_CLKCTRL_REG(prcm_base) |= 0x2; in start_uart_clk()293 CM_PER_UART4_CLKCTRL_REG(prcm_base) |= 0x2; in start_uart_clk()300 CM_PER_UART5_CLKCTRL_REG(prcm_base) |= 0x2; in start_uart_clk()[all …]
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