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Searched refs:psConfig (Results 1 – 22 of 22) sorted by relevance

/bsp/apollo2/libraries/drivers/hal/
A Dam_hal_cachectrl.c94 am_hal_cachectrl_enable(const am_hal_cachectrl_config_t *psConfig) in am_hal_cachectrl_enable() argument
318 am_hal_cachectrl_config(am_hal_cachectrl_config_t *psConfig) in am_hal_cachectrl_config() argument
327 AM_REG_CACHECTRL_CACHECFG_ENABLE( psConfig->ui32EnableCache ) | in am_hal_cachectrl_config()
328 AM_REG_CACHECTRL_CACHECFG_LRU( psConfig->ui32LRU ) | in am_hal_cachectrl_config()
330 (psConfig->ui32EnableNCregions & 0x1) >> 0 ) | in am_hal_cachectrl_config()
332 (psConfig->ui32EnableNCregions & 0x2) >> 1 ) | in am_hal_cachectrl_config()
333 psConfig->ui32Config | in am_hal_cachectrl_config()
334 AM_REG_CACHECTRL_CACHECFG_SERIAL(psConfig->ui32SerialCacheMode) | in am_hal_cachectrl_config()
336 (psConfig->ui32FlashCachingEnables & 0x1) >> 0 ) | in am_hal_cachectrl_config()
338 (psConfig->ui32FlashCachingEnables & 0x2) >> 1 ) | in am_hal_cachectrl_config()
[all …]
A Dam_hal_tpiu.c203 am_hal_tpiu_configure(am_hal_tpiu_config_t *psConfig) in am_hal_tpiu_configure() argument
208 AM_REG(MCUCTRL, TPIUCTRL) |= psConfig->ui32TraceClkIn; in am_hal_tpiu_configure()
213 AM_REG(TPIU, SPPR) = psConfig->ui32PinProtocol; in am_hal_tpiu_configure()
219 AM_REG(TPIU, CSPSR) = (1 << (psConfig->ui32ParallelPortSize - 1)); in am_hal_tpiu_configure()
224 AM_REG(TPIU, ACPR) = psConfig->ui32ClockPrescaler; in am_hal_tpiu_configure()
251 am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig) in am_hal_tpiu_enable() argument
255 ui32ITMbitrate = psConfig->ui32SetItmBaud; in am_hal_tpiu_enable()
329 AM_REG(TPIU, ACPR) = psConfig->ui32ClockPrescaler; in am_hal_tpiu_enable()
335 AM_REG(TPIU, SPPR) = psConfig->ui32PinProtocol; in am_hal_tpiu_enable()
342 AM_REG(TPIU, CSPSR) = (1 << (psConfig->ui32ParallelPortSize - 1)); in am_hal_tpiu_enable()
[all …]
A Dam_hal_wdt.c88 am_hal_wdt_init(const am_hal_wdt_config_t *psConfig) in am_hal_wdt_init() argument
92 bool bResetEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_RESET; in am_hal_wdt_init()
93 bool bInterruptEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_INTERRUPT; in am_hal_wdt_init()
98 ui16IntCount = psConfig->ui16InterruptCount; in am_hal_wdt_init()
99 ui16ResetCount = psConfig->ui16ResetCount; in am_hal_wdt_init()
105 ui32ConfigVal = psConfig->ui32Config & ~(AM_REG_WDT_CFG_INTVAL_M | AM_REG_WDT_CFG_RESVAL_M); in am_hal_wdt_init()
153 if ( !(psConfig->ui32Config & AM_REG_WDT_CFG_CLKSEL_M) ) in am_hal_wdt_init()
A Dam_hal_adc.c105 am_hal_adc_config(am_hal_adc_config_t *psConfig) in am_hal_adc_config() argument
110 AM_REG(ADC, CFG) = (psConfig->ui32Clock | in am_hal_adc_config()
111 psConfig->ui32TriggerConfig | in am_hal_adc_config()
112 psConfig->ui32Reference | in am_hal_adc_config()
113 psConfig->ui32ClockMode | in am_hal_adc_config()
114 psConfig->ui32PowerMode | in am_hal_adc_config()
115 psConfig->ui32Repeat | in am_hal_adc_config()
A Dam_hal_pdm.c68 am_hal_pdm_config(am_hal_pdm_config_t *psConfig) in am_hal_pdm_config() argument
73 AM_REG(PDM, PCFG) = psConfig->ui32PDMConfigReg; in am_hal_pdm_config()
78 AM_REG(PDM, VCFG) = psConfig->ui32VoiceConfigReg; in am_hal_pdm_config()
83 AM_REG(PDM, FTHR) = psConfig->ui32FIFOThreshold; in am_hal_pdm_config()
A Dam_hal_vcomp.c67 am_hal_vcomp_config(const am_hal_vcomp_config_t *psConfig) in am_hal_vcomp_config() argument
73 AM_REG(VCOMP, CFG) = (psConfig->ui32LevelSelect | in am_hal_vcomp_config()
74 psConfig->ui32PosInput | in am_hal_vcomp_config()
75 psConfig->ui32NegInput); in am_hal_vcomp_config()
A Dam_hal_ios.c199 am_hal_ios_config(am_hal_ios_config_t *psConfig) in am_hal_ios_config() argument
208 g_pui8FIFOBase = (uint8_t *)(REG_IOSLAVE_BASEADDR + psConfig->ui32FIFOBase); in am_hal_ios_config()
209 g_pui8FIFOEnd = (uint8_t *)(REG_IOSLAVE_BASEADDR + psConfig->ui32RAMBase); in am_hal_ios_config()
211 g_ui32FifoBaseOffset = psConfig->ui32FIFOBase; in am_hal_ios_config()
216 ui32LRAMConfig = AM_REG_IOSLAVE_FIFOCFG_ROBASE(psConfig->ui32ROBase >> 3); in am_hal_ios_config()
217 ui32LRAMConfig |= AM_REG_IOSLAVE_FIFOCFG_FIFOBASE(psConfig->ui32FIFOBase >> 3); in am_hal_ios_config()
218 ui32LRAMConfig |= AM_REG_IOSLAVE_FIFOCFG_FIFOMAX(psConfig->ui32RAMBase >> 3); in am_hal_ios_config()
229 AM_REG(IOSLAVE, CFG) = psConfig->ui32InterfaceSelect; in am_hal_ios_config()
245 am_hal_ios_fifo_ptr_set(psConfig->ui32FIFOBase); in am_hal_ios_config()
250 AM_REG(IOSLAVE, FIFOTHR) = psConfig->ui32FIFOThreshold; in am_hal_ios_config()
A Dam_hal_tpiu.h178 extern void am_hal_tpiu_configure(am_hal_tpiu_config_t *psConfig);
179 extern void am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig);
A Dam_hal_cachectrl.h194 extern void am_hal_cachectrl_enable(const am_hal_cachectrl_config_t *psConfig);
197 extern void am_hal_cachectrl_config(am_hal_cachectrl_config_t *psConfig);
A Dam_hal_uart.c120 am_hal_uart_config(uint32_t ui32Module, am_hal_uart_config_t *psConfig) in am_hal_uart_config() argument
128 config_baudrate(ui32Module, psConfig->ui32BaudRate, am_hal_clkgen_sysclk_get()); in am_hal_uart_config()
133 ui32ConfigVal |= psConfig->ui32DataBits; in am_hal_uart_config()
138 ui32ConfigVal |= psConfig->bTwoStopBits ? AM_REG_UART_LCRH_STP2_M : 0; in am_hal_uart_config()
143 ui32ConfigVal |= psConfig->ui32Parity; in am_hal_uart_config()
153 AM_REGn(UART, ui32Module, CR) |= psConfig->ui32FlowCtrl; in am_hal_uart_config()
A Dam_hal_iom.c940 am_hal_iom_config(uint32_t ui32Module, const am_hal_iom_config_t *psConfig) in am_hal_iom_config() argument
948 ui32Config = psConfig->ui32InterfaceMode; in am_hal_iom_config()
960 if ( psConfig->bSPHA ) in am_hal_iom_config()
965 if ( psConfig->bSPOL ) in am_hal_iom_config()
976 if ( psConfig->ui32ClockFrequency >= 16000000UL) in am_hal_iom_config()
1001 (AM_REG_IOMSTR_FIFOTHR_FIFOWTHR(psConfig->ui8WriteThreshold) | in am_hal_iom_config()
1002 AM_REG_IOMSTR_FIFOTHR_FIFORTHR(psConfig->ui8ReadThreshold)); in am_hal_iom_config()
1016 isRevB2() && (AM_HAL_IOM_I2CMODE == psConfig->ui32InterfaceMode)) in am_hal_iom_config()
1020 ui32ClkCfg = iom_get_i2c_workaround_clock_cfg(psConfig->ui32ClockFrequency); in am_hal_iom_config()
1034 ui32ClkCfg = iom_get_interface_clock_cfg(psConfig->ui32ClockFrequency, in am_hal_iom_config()
[all …]
A Dam_hal_ctimer.c441 am_hal_ctimer_config_t *psConfig) in am_hal_ctimer_config() argument
452 ui32ConfigVal = ( (psConfig->ui32TimerAConfig) | in am_hal_ctimer_config()
453 (psConfig->ui32TimerBConfig << 16) ); in am_hal_ctimer_config()
458 ui32ConfigVal |= psConfig->ui32Link ? AM_HAL_CTIMER_LINK : 0; in am_hal_ctimer_config()
A Dam_hal_wdt.h163 extern void am_hal_wdt_init(const am_hal_wdt_config_t *psConfig);
A Dam_hal_vcomp.h153 extern void am_hal_vcomp_config(const am_hal_vcomp_config_t *psConfig);
A Dam_hal_adc.h317 extern void am_hal_adc_config(am_hal_adc_config_t *psConfig);
A Dam_hal_ctimer.h217 am_hal_ctimer_config_t *psConfig);
A Dam_hal_ios.h321 extern void am_hal_ios_config(am_hal_ios_config_t *psConfig);
A Dam_hal_uart.h283 am_hal_uart_config_t *psConfig);
A Dam_hal_iom.h462 const am_hal_iom_config_t *psConfig);
/bsp/rm48x50/HALCoGen/include/
A Dusbdevice.h90 extern uint32 USBDCDConfigDescGetSize(const tConfigHeader *psConfig);
91 extern uint32 USBDCDConfigDescGetNum(const tConfigHeader *psConfig,
93 extern tDescriptorHeader *USBDCDConfigDescGet(const tConfigHeader *psConfig,
98 USBDCDConfigGetNumAlternateInterfaces(const tConfigHeader *psConfig,
101 USBDCDConfigGetInterface(const tConfigHeader *psConfig,
105 USBDCDConfigGetInterfaceEndpoint(const tConfigHeader *psConfig,
A Dusbdevicepriv.h48 const tConfigHeader *psConfig,
51 const tConfigHeader *psConfig,
A Dusblib.h1262 USBDescGetNumAlternateInterfaces(tConfigDescriptor *psConfig,
1264 extern tInterfaceDescriptor *USBDescGetInterface(tConfigDescriptor *psConfig,

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