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Searched refs:rcc_cfgr (Results 1 – 4 of 4) sorted by relevance

/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/
A Dsystem_n32g4fr.c310 uint32_t rcc_cfgr = 0; in SetSysClock() local
388 rcc_cfgr = RCC->CFG; in SetSysClock()
389 rcc_cfgr |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI_DIV2 : RCC_CFG_PLLSRC_HSE); in SetSysClock()
392 rcc_cfgr |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); in SetSysClock()
397 rcc_cfgr |= (PLL_MUL - 2) << 18; in SetSysClock()
399 rcc_cfgr |= ((PLL_MUL - 17) << 18) | (1 << 27); in SetSysClock()
402 RCC->CFG = rcc_cfgr; in SetSysClock()
/bsp/n32/libraries/N32G45x_Firmware_Library/CMSIS/device/
A Dsystem_n32g45x.c310 volatile uint32_t rcc_cfgr = 0; in SetSysClock() local
388 rcc_cfgr = RCC->CFG; in SetSysClock()
389 rcc_cfgr |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI_DIV2 : RCC_CFG_PLLSRC_HSE); in SetSysClock()
392 rcc_cfgr |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); in SetSysClock()
397 rcc_cfgr |= (PLL_MUL - 2) << 18; in SetSysClock()
399 rcc_cfgr |= ((PLL_MUL - 17) << 18) | (1 << 27); in SetSysClock()
402 RCC->CFG = rcc_cfgr; in SetSysClock()
/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/
A Dsystem_n32wb452.c310 uint32_t rcc_cfgr = 0; in SetSysClock() local
388 rcc_cfgr = RCC->CFG; in SetSysClock()
389 rcc_cfgr |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI_DIV2 : RCC_CFG_PLLSRC_HSE); in SetSysClock()
392 rcc_cfgr |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); in SetSysClock()
397 rcc_cfgr |= (PLL_MUL - 2) << 18; in SetSysClock()
399 rcc_cfgr |= ((PLL_MUL - 17) << 18) | (1 << 27); in SetSysClock()
402 RCC->CFG = rcc_cfgr; in SetSysClock()
/bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/
A Dsystem_n32g45x.c310 uint32_t rcc_cfgr = 0; in SetSysClock() local
388 rcc_cfgr = RCC->CFG; in SetSysClock()
389 rcc_cfgr |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI_DIV2 : RCC_CFG_PLLSRC_HSE); in SetSysClock()
392 rcc_cfgr |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2); in SetSysClock()
397 rcc_cfgr |= (PLL_MUL - 2) << 18; in SetSysClock()
399 rcc_cfgr |= ((PLL_MUL - 17) << 18) | (1 << 27); in SetSysClock()
402 RCC->CFG = rcc_cfgr; in SetSysClock()

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