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Searched refs:readl (Results 1 – 25 of 87) sorted by relevance

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/bsp/allwinner/libraries/sunxi-hal/hal/source/prcm/prcm-sun50iw11/
A Dreset.c42 writel(((readl(CCU_MSGBOX_BGR_REG) & (~(0x1 << 16))) | in ccu_set_mclk_reset()
47 writel(((readl(CCU_MSGBOX_BGR_REG) & (~(0x1 << 17))) | in ccu_set_mclk_reset()
52 writel(((readl(CCU_R_MSGBOX_BGR_REG) & (~(0x1 << 16))) | in ccu_set_mclk_reset()
61 writel(((readl(CCU_R_DMA_BGR_REG) & (~(0x1 << 16))) | in ccu_set_mclk_reset()
113 writel(((readl(CCU_SPINLOCK_BGR_REG) & (~(0x1 << 16))) in ccu_set_mclk_reset()
119 writel(((readl(CCU_MSGBOX_BGR_REG) & (~(0x1 << 16))) in ccu_set_mclk_reset()
150 writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 0))) | in ccu_set_mclk_reset()
157 writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 0))) | in ccu_set_mclk_reset()
165 writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 1))) | in ccu_set_mclk_reset()
172 writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 1))) | in ccu_set_mclk_reset()
[all …]
A Dpower.c53 value = readl(C0_CPUX_POWEROFF_GATING_REG); in ccu_set_poweroff_gating_state()
61 value = readl(C0_CPUX_POWEROFF_GATING_REG); in ccu_set_poweroff_gating_state()
69 value = readl(C0_CPUX_POWEROFF_GATING_REG); in ccu_set_poweroff_gating_state()
118 value = readl(XO_CTRL_REG); in ccu_24mhosc_disable()
129 value = (readl(CCU_PLL_CTRL1) | (0xa7 << 24)); in ccu_24mhosc_disable()
131 value = (readl(CCU_PLL_CTRL1) | (0xa7 << 24)); in ccu_24mhosc_disable()
144 value = (readl(CCU_PLL_CTRL1) | (0xa7 << 24)); in ccu_24mhosc_enable()
146 value = (readl(CCU_PLL_CTRL1) | (0xa7 << 24)); in ccu_24mhosc_enable()
154 value = (readl(CCU_PLL_CTRL1) | (0xa7 << 24)); in ccu_24mhosc_enable()
156 value = (readl(CCU_PLL_CTRL1) | (0xa7 << 24)); in ccu_24mhosc_enable()
[all …]
A Dmclk.c198 writel(((readl(CCU_PSI_AHB1_AHB2_CFG_REG) & in ccu_set_mclk_src()
205 writel(((readl(CCU_PSI_AHB1_AHB2_CFG_REG) & in ccu_set_mclk_src()
212 writel(((readl(CCU_PSI_AHB1_AHB2_CFG_REG) & in ccu_set_mclk_src()
219 writel(((readl(CCU_PSI_AHB1_AHB2_CFG_REG) & in ccu_set_mclk_src()
805 value = readl(CCU_CPU_AXI_CFG_REG); in ccu_set_mclk_div()
814 value = readl(CCU_CPU_AXI_CFG_REG); in ccu_set_mclk_div()
831 value = readl(CCU_PSI_AHB1_AHB2_CFG_REG); in ccu_set_mclk_div()
847 value = readl(CCU_APB1_CFG_REG); in ccu_set_mclk_div()
863 value = readl(CCU_APB2_CFG_REG); in ccu_set_mclk_div()
1036 value = readl(CCU_CPU_AXI_CFG_REG); in ccu_get_mclk_div()
[all …]
A Dccu.c51 calibration_status = readl(IOSC_CLK_AUTO_CALI); in dcxo_cali_start()
52 xo_ctrl = readl(XO_CTRL); in dcxo_cali_start()
53 writel(readl(XO_CTRL) | (0xa), XO_CTRL); in dcxo_cali_start()
90 value = readl(IOSC_CLK_AUTO_CALI); in osc_freq_init()
138 value = readl(IOSC_CLK_AUTO_CALI); in osc_freq_filter()
229 return readl((unsigned long)reg); in read_rtc_domain_reg()
/bsp/ck802/drivers/
A Dpinmux.c27 #define readl(addr) \ macro
44 value = readl(PHOBOS_GIPO0_PORTCTL_REG); in phobos_ioreuse_initial()
48 value = readl(PHOBOS_GIPO1_PORTCTL_REG); in phobos_ioreuse_initial()
53 value = readl(PHOBOS_IOMUX0L_REG); in phobos_ioreuse_initial()
57 value = readl(PHOBOS_IOMUX0H_REG); in phobos_ioreuse_initial()
61 value = readl(PHOBOS_IOMUX1L_REG); in phobos_ioreuse_initial()
76 value = readl(PHOBOS_IOMUX0L_REG); in phobos_pwm_ioreuse()
126 val = readl(PHOBOS_IOMUX1L_REG); in pin_mux()
135 val = readl(PHOBOS_GIPO0_PORTCTL_REG); in pin_mux()
144 val = readl(PHOBOS_IOMUX0H_REG); in pin_mux()
[all …]
/bsp/dm365/platform/
A Dpsc.c33 if ((readl(mdstat) & 0x1f) == state) in psc_change_state()
39 while (readl(PSC_PTSTAT) & 1) ; in psc_change_state()
44 writel(readl(mdctl) & (~0x1f), mdctl); in psc_change_state()
45 writel(readl(mdctl) | state, mdctl); in psc_change_state()
50 writel(readl(PSC_PTCMD) | 1, PSC_PTCMD); in psc_change_state()
55 while (readl(PSC_PTSTAT) & 1) ; in psc_change_state()
/bsp/allwinner/libraries/sunxi-hal/hal/source/tpadc/
A Dhal_tpadc.c30 reg_val = readl(reg_base + TP_INT_FIFOC); in sunxi_flush_fifo()
53 reg_val = readl(reg_base + TP_CTRL0); in sunxi_set_acqiure_time()
63 reg_val = readl(reg_base + TP_CTRL0); in sunxi_set_frequency_divider()
73 reg_val = readl(reg_base + TP_CTRL0); in sunxi_set_clk_divider()
83 reg_val = readl(reg_base + TP_CTRL0); in sunxi_select_delay_mode()
93 reg_val = readl(reg_base + TP_CTRL0); in sunxi_set_dealy_time()
112 reg_val = readl(reg_base + TP_CTRL1); in sunxi_tpadc_adc_ch_select()
140 reg_val = readl(reg_base + TP_CTRL1); in sunxi_tpadc_mode_select()
151 reg_val = readl(reg_base + TP_CTRL1); in sunxi_tpadc_enable()
161 reg_val = readl(reg_base + TP_CTRL1); in sunxi_set_up_debou_time()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/
A Dclk_periph.c52 reg = readl(periph->mux.reg); in sunxi_clk_periph_get_parent()
79 reg = readl(periph->mux.reg); in sunxi_clk_periph_set_parent()
140 reg = readl(gate->reset); in __sunxi_clk_periph_enable()
148 reg = readl(gate->bus); in __sunxi_clk_periph_enable()
167 reg = readl(gate->dram); in __sunxi_clk_periph_enable()
220 reg = readl(gate->bus); in sunxi_clk_periph_is_enabled()
241 reg = readl(gate->dram); in sunxi_clk_periph_is_enabled()
308 reg = readl(gate->dram); in __sunxi_clk_periph_disable()
328 reg = readl(gate->bus); in __sunxi_clk_periph_disable()
388 reg = readl(divider->reg); in sunxi_clk_periph_recalc_rate()
[all …]
A Dclk_factors.c77 reg = readl(factor->pll_lock_ctrl_reg); in sunxi_clk_is_lock()
81 reg = readl(factor->pll_lock_ctrl_reg); in sunxi_clk_is_lock()
88 reg = readl(factor->lock_reg); in sunxi_clk_is_lock()
135 reg = readl(factor->reg); in sunxi_clk_fators_enable()
140 reg = readl(factor->reg); in sunxi_clk_fators_enable()
150 reg = readl(factor->reg); in sunxi_clk_fators_enable()
209 reg = readl(factor->reg); in sunxi_clk_fators_disable()
225 reg = readl(factor->reg); in sunxi_clk_fators_disable()
266 reg = readl(factor->reg); in sunxi_clk_fators_is_enabled()
297 reg = readl(factor->reg); in sunxi_clk_factors_recalc_rate()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/gpadc/
A Dhal_gpadc.c232 reg_val = readl((unsigned long)(reg_base) + GP_SR_REG); in gpadc_sample_rate_set()
241 reg_val = readl((unsigned long)(reg_base) + GP_CTRL_REG); in gpadc_calibration_enable()
251 reg_val = readl((unsigned long)(reg_base) + GP_CTRL_REG); in gpadc_mode_select()
262 reg_val = readl((unsigned long)(reg_base) + GP_CTRL_REG); in gpadc_enable()
272 reg_val = readl((unsigned long)(reg_base) + GP_CTRL_REG); in gpadc_disable()
279 return readl((unsigned long)(reg_base) + GP_DATA_INTC_REG); in gpadc_read_channel_irq_enable()
284 return readl((unsigned long)(reg_base) + GP_DATAL_INTC_REG); in gpadc_read_channel_lowirq_enable()
289 return readl((unsigned long)(reg_base) + GP_DATAH_INTC_REG); in gpadc_read_channel_highirq_enable()
294 return readl((unsigned long)(reg_base) + GP_DATA_INTS_REG); in gpadc_channel_irq_status()
304 return readl((unsigned long)(reg_base) + GP_DATAL_INTS_REG); in gpadc_channel_lowirq_status()
[all …]
/bsp/k230/drivers/interdrv/adc/
A Ddrv_adc.c49 reg = readl(&adc_regs->trim_reg); in k230_adc_hw_init()
53 reg = readl(&adc_regs->trim_reg); in k230_adc_hw_init()
57 reg = readl(&adc_regs->trim_reg); in k230_adc_hw_init()
93 reg = readl(&adc_regs->trim_reg); in k_adc_drv_enabled()
104 reg = readl(&adc_regs->trim_reg); in k_adc_drv_disabled()
142 while ((readl(&kd_adc->adc_regs->cfg_reg) & 0x10000) == 0); in k230_get_adc_value()
143 *value = readl(&kd_adc->adc_regs->data_reg[channel]); in k230_get_adc_value()
/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/
A Dde_clock.c79 reg_val = readl(de_clk_tbl[i].mod_div_adr + de1_base); in de_clk_set_div()
92 reg_val = readl(de_clk_tbl[i].mod_div_adr + de_base); in de_clk_set_div()
120 reg_val = readl(de_clk_tbl[i].ahb_reset_adr in __de_clk_enable()
132 readl(de_clk_tbl[i].ahb_gate_adr + de_base); in __de_clk_enable()
143 readl(de_clk_tbl[i].mod_adr + de_base); in __de_clk_enable()
154 readl(de_clk_tbl[i].dram_gate_adr in __de_clk_enable()
181 readl(de_clk_tbl[i].dram_gate_adr in __de_clk_disable()
193 readl(de_clk_tbl[i].mod_adr + de_base); in __de_clk_disable()
204 readl(de_clk_tbl[i].ahb_gate_adr + de_base); in __de_clk_disable()
219 reg_val = readl(de_clk_tbl[i].ahb_reset_adr in __de_clk_disable()
/bsp/allwinner/libraries/sunxi-hal/hal/source/twi/
A Dhal_twi.c90 unsigned int reg_val = readl(base_addr + reg_clk); in twi_clk_write_reg()
180 temp = readl(base_addr + TWI_CTL_REG); in twi_clear_irq_flag()
181 temp |= readl(base_addr + TWI_CTL_REG); in twi_clear_irq_flag()
232 unsigned int reg_val = readl(base_addr + reg); in twi_disable()
241 unsigned int reg_val = readl(base_addr + reg); in twi_enable()
246 readl(base_addr + reg)); in twi_enable()
392 port, readl(base_addr + TWI_STAT_REG)); in twi_stop()
405 port, readl(base_addr + TWI_LCR_REG)); in twi_stop()
737 unsigned int reg_val = readl(base_addr + reg); in twi_soft_reset()
829 reg_val = readl(base_addr + TWI_DRIVER_FIFOC); in twi_clear_txfifo()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/
A Dccu_sdm.c18 if (sdm->enable && !(readl(common->base + common->reg) & sdm->enable)) in ccu_sdm_helper_is_enabled()
23 return !!(readl(common->base + sdm->tuning_reg) & sdm->tuning_enable); in ccu_sdm_helper_is_enabled()
47 reg = readl(common->base + sdm->tuning_reg); in ccu_sdm_helper_enable()
52 reg = readl(common->base + common->reg); in ccu_sdm_helper_enable()
69 reg = readl(common->base + common->reg); in ccu_sdm_helper_disable()
74 reg = readl(common->base + sdm->tuning_reg); in ccu_sdm_helper_disable()
134 reg = readl(common->base + sdm->tuning_reg); in ccu_sdm_helper_read_rate()
A Dccu_frac.c18 return !(readl(common->base + common->reg) & cf->enable); in ccu_frac_helper_is_enabled()
33 reg = readl(common->base + common->reg); in ccu_frac_helper_enable()
50 reg = readl(common->base + common->reg); in ccu_frac_helper_disable()
82 reg = readl(common->base + common->reg); in ccu_frac_helper_read_rate()
116 reg = readl(common->base + common->reg); in ccu_frac_helper_set_rate()
/bsp/at91/at91sam9g45/drivers/
A Dboard.c79 if (readl(AT91C_DBGU_CSR) & AT91C_US_RXRDY) in rt_timer_handler()
84 if (readl(AT91C_PITC_PISR) & AT91C_PITC_PITS) in rt_timer_handler()
89 nr_ticks = PIT_PICNT(readl(AT91C_PITC_PIVR)); in rt_timer_handler()
101 while (PIT_CPIV(readl(AT91C_PITC_PIVR)) != 0) in at91sam9g45_pit_reset()
106 pit_cnt += pit_cycle * PIT_PICNT(readl(AT91C_PITC_PIVR)); in at91sam9g45_pit_reset()
109 rt_kprintf("PIT_MR=0x%08x\n", readl(AT91C_PITC_PIMR)); in at91sam9g45_pit_reset()
/bsp/allwinner/libraries/sunxi-hal/hal/source/cir/
A Dhal_cir.c80 int_flag = readl(cir->base + CIR_RXSTA); in sunxi_cir_handler()
115 reg_val = readl(cir->base + CIR_CTRL); in sunxi_cir_mode_enable()
133 reg_val = readl(cir->base + CIR_CTRL); in sunxi_cir_mode_config()
149 reg_val = readl(cir->base + CIR_CONFIG); in sunxi_cir_sample_clock_select()
170 reg_val = readl(cir->base + CIR_CONFIG); in sunxi_cir_sample_noise_threshold()
186 reg_val = readl(cir->base + CIR_CONFIG); in sunxi_cir_sample_idle_threshold()
202 reg_val = readl(cir->base + CIR_CONFIG); in sunxi_cir_sample_active_threshold()
236 reg_val = readl(cir->base + CIR_RXINT); in sunxi_cir_fifo_level()
252 reg_val = readl(cir->base + CIR_RXINT); in sunxi_cir_irq_enable()
269 reg_val = readl(cir->base + CIR_RXINT); in sunxi_cir_irq_disable()
[all …]
/bsp/zynqmp-a53-dfzu2eg/drivers/
A Ddrv_uart.c91 mode_reg = readl(base + XUARTPS_MR_OFFSET); in _uart_baudrate_init()
140 temp_reg = (((readl(base + XUARTPS_CR_OFFSET)) & ((rt_uint32_t)(~XUARTPS_CR_EN_DIS_MASK))) | in _uart_baudrate_init()
152 temp_reg = (((readl(base + XUARTPS_CR_OFFSET)) & ((rt_uint32_t)(~XUARTPS_CR_EN_DIS_MASK))) | in _uart_baudrate_init()
173 mode_reg = readl(uart->hw_base + XUARTPS_MR_OFFSET); in zynqmp_uart_configure()
271 while ((readl(uart->hw_base + XUARTPS_SR_OFFSET) & in zynqmp_uart_putc()
290 if ((readl(uart->hw_base + XUARTPS_SR_OFFSET) & in zynqmp_uart_getc()
296 int ch = readl(uart->hw_base + XUARTPS_FIFO_OFFSET); in zynqmp_uart_getc()
322 isr_status = readl(uart->hw_base + XUARTPS_IMR_OFFSET); in rt_hw_uart_isr()
323 isr_status &= readl(uart->hw_base + XUARTPS_ISR_OFFSET); in rt_hw_uart_isr()
/bsp/cvitek/drivers/libraries/
A Dmmio.h37 #define readl(c) ({ u32 __v; __io_br(); __v = __raw_readl(c); __io_ar(__v); __v; }) macro
61 #define readl(a) __raw_readl(a) macro
104 return readl((void *) addr); in mmio_read_32()
119 writel(readl((void *) addr) & ~clear , (void *) addr); in mmio_clrbits_32()
124 writel(readl((void *) addr) | set , (void *) addr); in mmio_setbits_32()
130 writel((readl((void *) addr) & ~clear) | set , (void *) addr); in mmio_clrsetbits_32()
142 #define ioread32 readl
/bsp/ultrarisc/drivers/
A Ddrv_dw_spi.c120 tx_room = dw_spi_dev->fifo_len - (rt_uint32_t)(readl(&regs->txflr)); in tx_max()
147 rt_uint32_t val = readl(&regs->rxflr); in rx_max()
184 rxw = readl(&regs->dr); in dw_spi_reader()
206 status = readl(&regs->sr); in wait_for_idle()
273 if (cr0 != readl(&regs->ctrl0)) in _dw_spixfer()
307 readl(&regs->icr); in dw_spi_hw_init()
313 dw_spi_dev->version = readl(&regs->version); in dw_spi_hw_init()
325 if (fifo != readl(&regs->txftlr)) in dw_spi_hw_init()
335 rt_uint32_t cr0, tmp = readl(&regs->ctrl0); in dw_spi_hw_init()
339 cr0 = readl(&regs->ctrl0); in dw_spi_hw_init()
/bsp/allwinner/libraries/sunxi-hal/hal/source/timer/
A Dsunxi_htimer.c64 uint32_t old = readl(HTIMER_CNTVAL_LO_REG(timer)); in sunxi_htimer_sync()
66 while ((old - readl(HTIMER_CNTVAL_LO_REG(timer))) < HTIMER_SYNC_TICKS) in sunxi_htimer_sync()
76 uint32_t val = readl(HTIMER_CTL_REG(timer)); in sunxi_htimer_stop()
85 uint32_t val = readl(HTIMER_CTL_REG(timer)); in sunxi_htimer_start()
163 val = readl(HTIMER_CTL_REG(i)); in sunxi_htimer_init()
192 val = readl(HTIMER_IRQ_EN_REG); in sunxi_htimer_init()
/bsp/allwinner_tina/drivers/
A Ddrv_gpio.c46 data = readl(addr); in gpio_set_func()
73 data = readl(addr); in gpio_set_value()
94 data = readl(addr); in gpio_get_value()
119 data = readl(addr); in gpio_set_pull_mode()
147 data = readl(addr); in gpio_set_drive_level()
168 data = readl(addr); in gpio_direction_input()
189 data = readl(addr); in gpio_direction_output()
205 data = readl(addr); in gpio_ack_irq()
219 data = readl(addr); in gpio_select_irq_clock()
235 data = readl(addr); in gpio_set_debounce()
[all …]
/bsp/loongson/ls2kdev/drivers/ata/
A Ddwc_ahsata.c85 readl(b); \
124 cap_save = readl(&host_mmio->cap); in ahci_host_init()
128 tmp = readl(&host_mmio->ghc); in ahci_host_init()
185 tmp = readl(&port_mmio->cmd); in ahci_host_init()
221 tmp = readl(&port_mmio->cmd); in ahci_host_init()
262 tmp = readl(&port_mmio->serr); in ahci_host_init()
268 tmp = readl(&host_mmio->is); in ahci_host_init()
281 tmp = readl(&port_mmio->ssts); in ahci_host_init()
289 tmp = readl(&host_mmio->ghc); in ahci_host_init()
293 tmp = readl(&host_mmio->ghc); in ahci_host_init()
[all …]
/bsp/ultrarisc/arch/ur-cp100/
A Dplic.c60 rt_uint32_t val = readl(enable); in plic_irq_enable()
74 rt_uint32_t val = readl(enable); in plic_irq_disable()
111 return readl(claim); in plic_claim()
185 ie[i] = readl(enable_base + i * sizeof(rt_uint32_t)); in is_irqs_pending()
189 rt_uint32_t pending_irqs = readl(pending_base + i * sizeof(rt_uint32_t)) & ie[i]; in is_irqs_pending()
/bsp/allwinner/libraries/sunxi-hal/hal/source/hwspinlock/
A Dhal_hwspinlock.c18 return !!(readl(SPINLOCK_STATUS_REG) & (1 << num)); in hal_hwspinlock_check_taken()
25 while (readl(addr) != 0); in hal_hwspinlock_get()

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