Home
last modified time | relevance | path

Searched refs:refdiv (Results 1 – 7 of 7) sorted by relevance

/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_pllctl_drv.c87 uint32_t freq, fbdiv, refdiv, postdiv; in pllctl_init_int_pll_with_freq() local
99 refdiv--; in pllctl_init_int_pll_with_freq()
103 refdiv--; in pllctl_init_int_pll_with_freq()
110 refdiv++; in pllctl_init_int_pll_with_freq()
114 refdiv++; in pllctl_init_int_pll_with_freq()
121 if ((refdiv > PLLCTL_PLL_MAX_REFDIV) in pllctl_init_int_pll_with_freq()
168 refdiv--; in pllctl_init_frac_pll_with_freq()
172 refdiv--; in pllctl_init_frac_pll_with_freq()
179 refdiv++; in pllctl_init_frac_pll_with_freq()
183 refdiv++; in pllctl_init_frac_pll_with_freq()
[all …]
/bsp/rockchip/rk3500/driver/clk/
A Dclk-pll-rk3568.c175 rate_table->refdiv = fin_hz / clk_gcd; in rk_pll_clk_set_by_auto()
183 rate_table->refdiv = fin_hz / MHZ / clk_gcd; in rk_pll_clk_set_by_auto()
190 fin_64 = fin_64 / rate_table->refdiv; in rk_pll_clk_set_by_auto()
257 (rate->postdiv2 << PLLCON1_POSTDIV2_SHIFT | rate->refdiv << PLLCON1_REFDIV_SHIFT)); in rk_pll_set_rate()
285 rt_uint32_t refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; in rk_pll_get_rate() local
306 refdiv = (con & PLLCON1_REFDIV_MASK) >> PLLCON1_REFDIV_SHIFT; in rk_pll_get_rate()
310 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rk_pll_get_rate()
316 rt_do_div(frac_rate, refdiv); in rk_pll_get_rate()
A Dclk-pll-rk3588.c207 rate_table->refdiv = fin_hz / clk_gcd; in rk_pll_clk_set_by_auto()
215 rate_table->refdiv = fin_hz / MHZ / clk_gcd; in rk_pll_clk_set_by_auto()
222 fin_64 = fin_64 / rate_table->refdiv; in rk_pll_clk_set_by_auto()
352 … (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT | rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT)); in rk3036_pll_set_rate()
380 rt_uint32_t refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; in rk3036_pll_get_rate() local
401 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >> RK3036_PLLCON1_REFDIV_SHIFT; in rk3036_pll_get_rate()
405 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rk3036_pll_get_rate()
411 rt_do_div(frac_rate, refdiv); in rk3036_pll_get_rate()
A Dclk-rk3568.h42 rt_uint32_t refdiv; member
94 .refdiv = _refdiv, \
A Dclk-rk3588.h47 rt_uint32_t refdiv; member
119 .refdiv = _refdiv, \
/bsp/k230/drivers/interdrv/sysctl/sysctl_clock/
A Dsysctl_clk.c531 uint32_t refdiv; /* reference clock divide */ in sysctl_boot_get_root_clk_freq() local
555 refdiv = (sysctl_boot->pll[0].cfg0 >> 16) & 0x3F; /* bit 16~21 */ in sysctl_boot_get_root_clk_freq()
558 … freq = (double)OSC_CLOCK_FREQ_24M * (double)(fbdiv+1) / (double)(refdiv+1) / (double)(outdiv+1); in sysctl_boot_get_root_clk_freq()
584 refdiv = (sysctl_boot->pll[1].cfg0 >> 16) & 0x3F; /* bit 16~21 */ in sysctl_boot_get_root_clk_freq()
587 … freq = (double)OSC_CLOCK_FREQ_24M * (double)(fbdiv+1) / (double)(refdiv+1) / (double)(outdiv+1); in sysctl_boot_get_root_clk_freq()
613 refdiv = (sysctl_boot->pll[2].cfg0 >> 16) & 0x3F; /* bit 16~21 */ in sysctl_boot_get_root_clk_freq()
616 … freq = (double)OSC_CLOCK_FREQ_24M * (double)(fbdiv+1) / (double)(refdiv+1) / (double)(outdiv+1); in sysctl_boot_get_root_clk_freq()
642 refdiv = (sysctl_boot->pll[3].cfg0 >> 16) & 0x3F; /* bit 16~21 */ in sysctl_boot_get_root_clk_freq()
645 … freq = (double)OSC_CLOCK_FREQ_24M * (double)(fbdiv+1) / (double)(refdiv+1) / (double)(outdiv+1); in sysctl_boot_get_root_clk_freq()
672 bool sysctl_boot_set_root_clk_freq(sysctl_clk_node_e clk, uint32_t fbdiv, uint32_t refdiv, uint32_t… in sysctl_boot_set_root_clk_freq() argument
[all …]
A Dsysctl_clk.h568 bool sysctl_boot_set_root_clk_freq(sysctl_clk_node_e clk, uint32_t fbdiv, uint32_t refdiv, uint32_t…

Completed in 19 milliseconds