Searched refs:reg1 (Results 1 – 8 of 8) sorted by relevance
| /bsp/hifive1/freedom-e-sdk/bsp/include/sifive/ |
| A D | smp.h | 19 csrr reg1, mhartid ;\
34 #define smp_pause(reg1, reg2) \ argument
41 li reg1, CLINT_CTRL_ADDR ;\
44 sw reg2, 0(reg1) ;\
45 addi reg1, reg1, 4 ;\
47 blt reg1, reg2, 41b ;\
53 li reg1, CLINT_CTRL_ADDR ;\
56 add reg2, reg2, reg1 ;\
59 lw reg2, 0(reg1) ;\
61 addi reg1, reg1, 4 ;\
[all …]
|
| /bsp/sparkfun-redv/freedom-e-sdk/bsp/include/sifive/ |
| A D | smp.h | 34 #define smp_pause(reg1, reg2) \ argument
40 #define smp_resume(reg1, reg2) \ argument
41 li reg1, CLINT_CTRL_ADDR ;\
44 sw reg2, 0(reg1) ;\
45 addi reg1, reg1, 4 ;\
47 blt reg1, reg2, 41b ;\
53 li reg1, CLINT_CTRL_ADDR ;\
56 add reg2, reg2, reg1 ;\
59 lw reg2, 0(reg1) ;\
61 addi reg1, reg1, 4 ;\
[all …]
|
| /bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/ |
| A D | hal_fll_pi.c | 90 uint32_t reg1; in pi_fll_set_frequency() local
99 reg1 = FLL_CTRL[which_fll].FLL_CONF1; in pi_fll_set_frequency()
103 reg1 &= ~FLL_CTRL_CONF1_CLK_OUT_DIV_MASK; in pi_fll_set_frequency()
104 reg1 |= FLL_CTRL_CONF1_CLK_OUT_DIV(div); in pi_fll_set_frequency()
106 FLL_CTRL[which_fll].FLL_CONF1 = reg1; in pi_fll_set_frequency()
121 uint32_t reg1; in pi_fll_init() local
126 reg1 = FLL_CTRL[which_fll].FLL_CONF1; in pi_fll_init()
134 if (!READ_FLL_CTRL_CONF1_MODE(reg1)) { in pi_fll_init()
159 reg1 &= ~FLL_CTRL_CONF1_MODE_MASK; in pi_fll_init()
160 reg1 |= FLL_CTRL_CONF1_MODE(1); in pi_fll_init()
[all …]
|
| A D | hal_fll.c | 102 fll_reg_conf1_t reg1 = { in __fll_init() local
108 if (reg1.mode == 0) { in __fll_init()
155 reg1.output_lock_enable = 1; in __fll_init()
156 reg1.mode = 1; in __fll_init()
157 writew(reg1.raw, (uintptr_t)(PULP_FLL_ADDR + FLL_CONF1_OFFSET + in __fll_init()
167 freq = __rt_fll_get_freq_from_mult_div(reg1.mult_factor, in __fll_init()
168 reg1.clock_out_divider); in __fll_init()
193 fll_reg_conf1_t reg1 = { in __rt_fll_set_freq() local
199 reg1.mult_factor = mult; in __rt_fll_set_freq()
200 reg1.clock_out_divider = div; in __rt_fll_set_freq()
[all …]
|
| /bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/ |
| A D | gd32vf103_spi.c | 677 uint32_t reg1 = SPI_STAT(spi_periph); in spi_i2s_interrupt_flag_get() local
683 reg1 = reg1 & SPI_STAT_TBE; in spi_i2s_interrupt_flag_get()
688 reg1 = reg1 & SPI_STAT_RBNE; in spi_i2s_interrupt_flag_get()
693 reg1 = reg1 & SPI_STAT_RXORERR; in spi_i2s_interrupt_flag_get()
698 reg1 = reg1 & SPI_STAT_CONFERR; in spi_i2s_interrupt_flag_get()
703 reg1 = reg1 & SPI_STAT_CRCERR; in spi_i2s_interrupt_flag_get()
708 reg1 = reg1 & SPI_STAT_TXURERR; in spi_i2s_interrupt_flag_get()
713 reg1 = reg1 & SPI_STAT_FERR; in spi_i2s_interrupt_flag_get()
720 if((0U != reg1) && (0U != reg2)){ in spi_i2s_interrupt_flag_get()
|
| /bsp/at91/at91sam9260/drivers/ |
| A D | at91_nand.c | 89 uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; in nand_calculate_ecc() local
93 reg1 = reg2 = reg3 = 0; in nand_calculate_ecc()
100 reg1 ^= (idx & 0x3f); in nand_calculate_ecc()
137 ecc_code[2] = ((~reg1) << 2) | 0x03; in nand_calculate_ecc()
|
| /bsp/raspberry-pi/raspi4-64/drivers/ |
| A D | drv_eth.c | 341 rt_uint32_t reg1 = read32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL); in bcmgenet_adjust_link() local
345 reg1 |= (RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); in bcmgenet_adjust_link()
346 write32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL, reg1); in bcmgenet_adjust_link()
|
| /bsp/raspberry-pi/raspi4-32/driver/ |
| A D | drv_eth.c | 349 rt_uint32_t reg1 = read32(MAC_REG + EXT_RGMII_OOB_CTRL); in bcmgenet_adjust_link() local
353 reg1 |= (RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); in bcmgenet_adjust_link()
354 write32(MAC_REG + EXT_RGMII_OOB_CTRL, reg1); in bcmgenet_adjust_link()
|
Completed in 19 milliseconds