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Searched refs:regValue (Results 1 – 21 of 21) sorted by relevance

/bsp/Infineon/libraries/templates/XMC7200D/libs/TARGET_APP_KIT_XMC72_EVK/COMPONENT_CM0P/
A Dsystem_cm0plus.c398 uint32_t regValue = 0u; in Cy_SysGetCM7Status() local
417 return (regValue); in Cy_SysGetCM7Status()
425 uint32_t regValue; in Cy_SysEnableCM7() local
452 CPUSS->CM7_0_PWR_CTL = regValue; in Cy_SysEnableCM7()
470 CPUSS->CM7_1_PWR_CTL = regValue; in Cy_SysEnableCM7()
487 uint32_t regValue; in Cy_SysDisableCM7() local
496 CPUSS->CM7_0_PWR_CTL = regValue; in Cy_SysDisableCM7()
509 CPUSS->CM7_1_PWR_CTL = regValue; in Cy_SysDisableCM7()
523 uint32_t regValue; in Cy_SysRetainCM7() local
552 uint32_t regValue; in Cy_SysResetCM7() local
[all …]
/bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/
A Dsystem_cm0plus.c389 uint32_t regValue = 0u; in Cy_SysGetCM7Status() local
408 return (regValue); in Cy_SysGetCM7Status()
416 uint32_t regValue; in Cy_SysEnableCM7() local
443 CPUSS->CM7_0_PWR_CTL = regValue; in Cy_SysEnableCM7()
461 CPUSS->CM7_1_PWR_CTL = regValue; in Cy_SysEnableCM7()
478 uint32_t regValue; in Cy_SysDisableCM7() local
487 CPUSS->CM7_0_PWR_CTL = regValue; in Cy_SysDisableCM7()
500 CPUSS->CM7_1_PWR_CTL = regValue; in Cy_SysDisableCM7()
514 uint32_t regValue; in Cy_SysRetainCM7() local
543 uint32_t regValue; in Cy_SysResetCM7() local
[all …]
/bsp/Infineon/xmc7200-kit_xmc7200_evk/libs/TARGET_APP_KIT_XMC72_EVK/COMPONENT_CM0P/
A Dsystem_cm0plus.c398 uint32_t regValue = 0u; in Cy_SysGetCM7Status() local
417 return (regValue); in Cy_SysGetCM7Status()
425 uint32_t regValue; in Cy_SysEnableCM7() local
452 CPUSS->CM7_0_PWR_CTL = regValue; in Cy_SysEnableCM7()
470 CPUSS->CM7_1_PWR_CTL = regValue; in Cy_SysEnableCM7()
487 uint32_t regValue; in Cy_SysDisableCM7() local
496 CPUSS->CM7_0_PWR_CTL = regValue; in Cy_SysDisableCM7()
509 CPUSS->CM7_1_PWR_CTL = regValue; in Cy_SysDisableCM7()
523 uint32_t regValue; in Cy_SysRetainCM7() local
552 uint32_t regValue; in Cy_SysResetCM7() local
[all …]
/bsp/Infineon/psoc6-cy8ckit-062S2-43012/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/
A Dsystem_psoc6_cm0plus.c278 uint32_t regValue; in Cy_SysGetCM4Status() local
283 return (regValue); in Cy_SysGetCM4Status()
301 uint32_t regValue; in Cy_SysEnableCM4() local
320 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysEnableCM4()
349 uint32_t regValue; in Cy_SysDisableCM4() local
356 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysDisableCM4()
387 uint32_t regValue; in Cy_SysRetainCM4() local
394 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysRetainCM4()
419 uint32_t regValue; in Cy_SysResetCM4() local
425 regValue |= CY_SYS_CM4_STATUS_RESET; in Cy_SysResetCM4()
[all …]
/bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_CM0P/
A Dsystem_psoc6_cm0plus.c278 uint32_t regValue; in Cy_SysGetCM4Status() local
283 return (regValue); in Cy_SysGetCM4Status()
301 uint32_t regValue; in Cy_SysEnableCM4() local
320 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysEnableCM4()
349 uint32_t regValue; in Cy_SysDisableCM4() local
356 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysDisableCM4()
387 uint32_t regValue; in Cy_SysRetainCM4() local
394 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysRetainCM4()
419 uint32_t regValue; in Cy_SysResetCM4() local
425 regValue |= CY_SYS_CM4_STATUS_RESET; in Cy_SysResetCM4()
[all …]
/bsp/Infineon/libraries/templates/PSOC62/libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/
A Dsystem_psoc6_cm0plus.c278 uint32_t regValue; in Cy_SysGetCM4Status() local
283 return (regValue); in Cy_SysGetCM4Status()
301 uint32_t regValue; in Cy_SysEnableCM4() local
320 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysEnableCM4()
349 uint32_t regValue; in Cy_SysDisableCM4() local
356 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysDisableCM4()
387 uint32_t regValue; in Cy_SysRetainCM4() local
394 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysRetainCM4()
419 uint32_t regValue; in Cy_SysResetCM4() local
425 regValue |= CY_SYS_CM4_STATUS_RESET; in Cy_SysResetCM4()
[all …]
/bsp/Infineon/psoc6-cy8ckit-062-BLE/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_CM0P/
A Dsystem_psoc6_cm0plus.c278 uint32_t regValue; in Cy_SysGetCM4Status() local
283 return (regValue); in Cy_SysGetCM4Status()
301 uint32_t regValue; in Cy_SysEnableCM4() local
320 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysEnableCM4()
349 uint32_t regValue; in Cy_SysDisableCM4() local
356 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysDisableCM4()
387 uint32_t regValue; in Cy_SysRetainCM4() local
394 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysRetainCM4()
419 uint32_t regValue; in Cy_SysResetCM4() local
425 regValue |= CY_SYS_CM4_STATUS_RESET; in Cy_SysResetCM4()
[all …]
/bsp/Infineon/psoc6-cy8ckit-062-WIFI-BT/libs/TARGET_CY8CKIT-062-WIFI-BT/COMPONENT_CM0P/
A Dsystem_psoc6_cm0plus.c278 uint32_t regValue; in Cy_SysGetCM4Status() local
283 return (regValue); in Cy_SysGetCM4Status()
301 uint32_t regValue; in Cy_SysEnableCM4() local
320 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysEnableCM4()
349 uint32_t regValue; in Cy_SysDisableCM4() local
356 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysDisableCM4()
387 uint32_t regValue; in Cy_SysRetainCM4() local
394 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysRetainCM4()
419 uint32_t regValue; in Cy_SysResetCM4() local
425 regValue |= CY_SYS_CM4_STATUS_RESET; in Cy_SysResetCM4()
[all …]
/bsp/Infineon/psoc6-cy8ckit-062s4/libs/TARGET_CY8CKIT-062S4/COMPONENT_CM0P/
A Dsystem_psoc6_cm0plus.c278 uint32_t regValue; in Cy_SysGetCM4Status() local
283 return (regValue); in Cy_SysGetCM4Status()
301 uint32_t regValue; in Cy_SysEnableCM4() local
320 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysEnableCM4()
349 uint32_t regValue; in Cy_SysDisableCM4() local
356 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysDisableCM4()
387 uint32_t regValue; in Cy_SysRetainCM4() local
394 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysRetainCM4()
419 uint32_t regValue; in Cy_SysResetCM4() local
425 regValue |= CY_SYS_CM4_STATUS_RESET; in Cy_SysResetCM4()
[all …]
/bsp/Infineon/psoc6-cy8cproto-062S3-4343W/libs/TARGET_CY8CPROTO-062S3-4343W/COMPONENT_CM0P/
A Dsystem_psoc6_cm0plus.c278 uint32_t regValue; in Cy_SysGetCM4Status() local
283 return (regValue); in Cy_SysGetCM4Status()
301 uint32_t regValue; in Cy_SysEnableCM4() local
320 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysEnableCM4()
349 uint32_t regValue; in Cy_SysDisableCM4() local
356 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysDisableCM4()
387 uint32_t regValue; in Cy_SysRetainCM4() local
394 CPUSS->CM4_PWR_CTL = regValue; in Cy_SysRetainCM4()
419 uint32_t regValue; in Cy_SysResetCM4() local
425 regValue |= CY_SYS_CM4_STATUS_RESET; in Cy_SysResetCM4()
[all …]
/bsp/nxp/imx/imxrt/libraries/drivers/
A Ddrv_rtl8211f.c194 rt_uint32_t regValue = 0U; in rt_phy_init() local
225 } while ((regValue != PHY_CONTROL_ID1) && (counter != 0U)); in rt_phy_init()
251 regValue |= PHY_RGMII_TX_DELAY_MASK; in rt_phy_init()
267 regValue |= PHY_RGMII_RX_DELAY_MASK; in rt_phy_init()
343 uint32_t regValue; in rt_phy_loopback() local
358 regValue = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; in rt_phy_loopback()
368 regValue &= ~PHY_BCTL_LOOP_MASK; in rt_phy_loopback()
380 uint32_t regValue; in get_link_status() local
386 if ((PHY_SSTATUS_LINKSTATUS_MASK & regValue) != 0U) in get_link_status()
405 uint32_t regValue; in get_link_speed_duplex() local
[all …]
/bsp/ft2004/libraries/bsp/ft_sd/
A Dft_sdctrl_option.c24 u32 regValue; in FSdCtrl_NormalIrqSet() local
29 …regValue = ((flgs & NORMAL_IRQ_CC) ? NORMAL_INT_EN_ECC : 0) | ((flgs & NORMAL_IRQ_CR) ? NORMAL_INT… in FSdCtrl_NormalIrqSet()
32 Ft_out32(pConfig->baseAddress + NORMAL_INT_EN_REG_OFFSET, regValue); in FSdCtrl_NormalIrqSet()
38 u32 regValue; in FsdCtrl_errorIrqSet() local
42 …regValue = ((flgs & ERROR_IRQ_CTE) ? ERROR_INT_EN_CTE : 0) | ((flgs & ERROR_IRQ_CCRCE) ? ERROR_INT… in FsdCtrl_errorIrqSet()
45 Ft_out32(pConfig->baseAddress + ERROR_INT_EN_REG_OFFSET, regValue); in FsdCtrl_errorIrqSet()
51 u32 regValue; in FSdCtrl_BdIrqSet() local
55 …regValue = ((flgs & BD_IRQ_TRS) ? BD_ISR_EN_ETRS : 0) | ((flgs & BD_IRQ_DTE) ? BD_ISR_EN_EDTE : 0)… in FSdCtrl_BdIrqSet()
60 Ft_out32(pConfig->baseAddress + BD_ISR_EN_REG_OFFSET, regValue); in FSdCtrl_BdIrqSet()
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_xrdc.c232 uint32_t regValue; in XRDC_SetMemAccessConfig() local
248 regValue = 0U; in XRDC_SetMemAccessConfig()
265 regValue |= config->policy[i]; in XRDC_SetMemAccessConfig()
275 regValue = 0U; in XRDC_SetMemAccessConfig()
282 regValue |= config->policy[i]; in XRDC_SetMemAccessConfig()
395 uint32_t regValue; in XRDC_SetPeriphAccessConfig() local
399 regValue = 0U; in XRDC_SetPeriphAccessConfig()
411 regValue |= config->policy[i]; in XRDC_SetPeriphAccessConfig()
419 base->PDAC_W[index][0U] = regValue; in XRDC_SetPeriphAccessConfig()
429 regValue = 0U; in XRDC_SetPeriphAccessConfig()
[all …]
/bsp/hpmicro/hpm6750evk/board/
A Dhpm_sgtl5000.c622 uint16_t regValue = 0U, regBitMask = 0x40U; in sgtl_set_play() local
627 regValue = 0x40U; in sgtl_set_play()
632 regValue = 0U; in sgtl_set_play()
635 return sgtl_modify_reg(context, CHIP_ANA_CTRL, regBitMask, regValue); in sgtl_set_play()
640 uint16_t regValue = 0U, regBitMask = 0x4U; in sgtl_set_record() local
645 regValue = 0x4U; in sgtl_set_record()
650 regValue = 0U; in sgtl_set_record()
653 return sgtl_modify_reg(context, CHIP_ANA_CTRL, regBitMask, regValue); in sgtl_set_record()
/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/
A Dhpm_sgtl5000.c571 uint16_t regValue = 0U, regBitMask = 0x40U; in sgtl_set_pay() local
575 regValue = 0x40U; in sgtl_set_pay()
578 regValue = 0U; in sgtl_set_pay()
581 return sgtl_modify_reg(context, CHIP_ANA_CTRL, regBitMask, regValue); in sgtl_set_pay()
586 uint16_t regValue = 0U, regBitMask = 0x4U; in sgtl_set_record() local
590 regValue = 0x4U; in sgtl_set_record()
593 regValue = 0U; in sgtl_set_record()
596 return sgtl_modify_reg(context, CHIP_ANA_CTRL, regBitMask, regValue); in sgtl_set_record()
/bsp/nxp/lpc/lpc54114-lite/drivers/audio/
A Dfsl_wm8904.c531 uint16_t regValue; in WM8904_ModifyRegister() local
533 result = WM8904_ReadRegister(handle, reg, &regValue); in WM8904_ModifyRegister()
539 regValue &= (uint16_t)~mask; in WM8904_ModifyRegister()
540 regValue |= value; in WM8904_ModifyRegister()
542 return WM8904_WriteRegister(handle, reg, regValue); in WM8904_ModifyRegister()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/
A Dbl702_romdriver.h438 …((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM…
440 …((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM…
442 …((int(*)(spi_flash_cfg_type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) R…
444 …((int(*)(spi_flash_cfg_type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) …
583 …((void (*)(struct spi_psram_cfg_type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_P…
585 …((void (*)(struct spi_psram_cfg_type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_P…
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/
A Dbl602_romdriver.h563 …((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM…
566 …((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM…
653 …((int(*)(spi_flash_cfg_type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) R…
656 …((int(*)(spi_flash_cfg_type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) …
/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_ETH_Driver/src/
A Dapm32f10x_eth.c189 uint32_t regValue = 0; in ETH_Config() local
266 regValue = ETH_ReadPHYRegister(addr, PHY_SR); in ETH_Config()
268 if ((regValue & PHY_DUPLEX_STATUS) != (uint32_t)RESET) in ETH_Config()
276 if (regValue & PHY_SPEED_STATUS) in ETH_Config()
/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_ETH_Driver/src/
A Dapm32f4xx_eth.c185 uint32_t regValue = 0; in ETH_Config() local
260 regValue = ETH_ReadPHYRegister(addr, PHY_SR); in ETH_Config()
262 if((regValue & PHY_DUPLEX_STATUS) != (uint32_t)RESET) in ETH_Config()
270 if(regValue & PHY_SPEED_STATUS) in ETH_Config()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/
A Dbl616_romdriver_e907.h1699 …((int (*) (spi_flash_cfg_type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_…
1702 …((int (*) (spi_flash_cfg_type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen))RO…
1729 …((int (*) (spi_flash_cfg_type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_…
1732 …((int (*) (spi_flash_cfg_type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen))R…

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