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Searched refs:reg_base (Results 1 – 25 of 125) sorted by relevance

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/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/
A Dbflb_uart.c13 reg_base = dev->reg_base; in bflb_uart_init()
126 reg_base = dev->reg_base; in bflb_uart_deinit()
141 reg_base = dev->reg_base; in bflb_uart_enable()
156 reg_base = dev->reg_base; in bflb_uart_disable()
170 reg_base = dev->reg_base; in bflb_uart_link_txdma()
185 reg_base = dev->reg_base; in bflb_uart_link_rxdma()
200 reg_base = dev->reg_base; in bflb_uart_putchar()
216 reg_base = dev->reg_base; in bflb_uart_getchar()
255 reg_base = dev->reg_base; in bflb_uart_txready()
267 reg_base = dev->reg_base; in bflb_uart_txempty()
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A Dbflb_wdg.c8 uint32_t reg_base; in bflb_wdg_init() local
10 reg_base = dev->reg_base; in bflb_wdg_init()
44 uint32_t reg_base; in bflb_wdg_start() local
46 reg_base = dev->reg_base; in bflb_wdg_start()
59 uint32_t reg_base; in bflb_wdg_stop() local
61 reg_base = dev->reg_base; in bflb_wdg_stop()
73 uint32_t reg_base; in bflb_wdg_get_countervalue() local
75 reg_base = dev->reg_base; in bflb_wdg_get_countervalue()
84 reg_base = dev->reg_base; in bflb_wdg_set_countervalue()
96 reg_base = dev->reg_base; in bflb_wdg_reset_countervalue()
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A Dbflb_sec_aes.c16 reg_base = dev->reg_base; in bflb_aes_init()
34 reg_base = dev->reg_base; in bflb_aes_deinit()
51 reg_base = dev->reg_base; in bflb_aes_set_mode()
73 reg_base = dev->reg_base; in bflb_aes_setkey()
145 reg_base = dev->reg_base; in bflb_aes_encrypt()
217 reg_base = dev->reg_base; in bflb_aes_decrypt()
282 reg_base = dev->reg_base; in bflb_aes_link_init()
301 reg_base = dev->reg_base; in bflb_aes_link_deinit()
319 reg_base = dev->reg_base; in bflb_aes_link_update()
361 reg_base = dev->reg_base; in bflb_group0_request_aes_access()
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A Dbflb_pwm_v2.c11 reg_base = dev->reg_base; in bflb_pwm_v2_init()
54 reg_base = dev->reg_base; in bflb_pwm_v2_deinit()
104 reg_base = dev->reg_base; in bflb_pwm_v2_set_period()
117 reg_base = dev->reg_base; in bflb_pwm_v2_start()
138 reg_base = dev->reg_base; in bflb_pwm_v2_stop()
160 reg_base = dev->reg_base; in bflb_pwm_v2_get_frequency()
194 reg_base = dev->reg_base; in bflb_pwm_v2_channel_init()
246 reg_base = dev->reg_base; in bflb_pwm_v2_channel_positive_start()
257 reg_base = dev->reg_base; in bflb_pwm_v2_channel_negative_start()
268 reg_base = dev->reg_base; in bflb_pwm_v2_channel_positive_stop()
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A Dbflb_mjpeg.c9 reg_base = dev->reg_base; in bflb_mjpeg_set_yuv422_interleave_order()
30 reg_base = dev->reg_base; in bflb_mjpeg_set_framesize()
44 reg_base = dev->reg_base; in bflb_mjpeg_init()
228 reg_base = dev->reg_base; in bflb_mjpeg_start()
240 reg_base = dev->reg_base; in bflb_mjpeg_stop()
252 reg_base = dev->reg_base; in bflb_mjpeg_sw_run()
279 reg_base = dev->reg_base; in bflb_mjpeg_kick_run()
313 reg_base = dev->reg_base; in bflb_mjpeg_kick_stop()
334 reg_base = dev->reg_base; in bflb_mjpeg_kick()
346 reg_base = dev->reg_base; in bflb_mjpeg_tcint_mask()
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A Dbflb_dbi.c36 reg_base = dev->reg_base; in bflb_dbi_init()
210 reg_base = dev->reg_base; in bflb_dbi_deinit()
229 reg_base = dev->reg_base; in bflb_dbi_qspi_set_addr()
250 reg_base = dev->reg_base; in bflb_dbi_fill_fifo()
278 reg_base = dev->reg_base; in bflb_dbi_get_words_cnt_form_pixel()
318 reg_base = dev->reg_base; in bflb_dbi_send_cmd_data()
407 reg_base = dev->reg_base; in bflb_dbi_send_cmd_read_data()
494 reg_base = dev->reg_base; in bflb_dbi_send_cmd_pixel()
576 reg_base = dev->reg_base; in bflb_dbi_link_txdma()
592 reg_base = dev->reg_base; in bflb_dbi_txint_mask()
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A Dbflb_i2c.c18 reg_base = dev->reg_base; in bflb_i2c_addr_config()
49 reg_base = dev->reg_base; in bflb_i2c_set_dir()
66 reg_base = dev->reg_base; in bflb_i2c_set_datalen()
81 reg_base = dev->reg_base; in bflb_i2c_set_frequence()
111 reg_base = dev->reg_base; in bflb_i2c_isbusy()
127 reg_base = dev->reg_base; in bflb_i2c_isend()
143 reg_base = dev->reg_base; in bflb_i2c_isnak()
159 reg_base = dev->reg_base; in bflb_i2c_enable()
171 reg_base = dev->reg_base; in bflb_i2c_disable()
194 reg_base = dev->reg_base; in bflb_i2c_isenable()
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A Dbflb_pwm_v1.c7 uint32_t reg_base; in bflb_pwm_v1_channel_init() local
11 reg_base = dev->reg_base; in bflb_pwm_v1_channel_init()
57 reg_base = dev->reg_base; in bflb_pwm_v1_channel_deinit()
101 reg_base = dev->reg_base; in bflb_pwm_v1_start()
123 reg_base = dev->reg_base; in bflb_pwm_v1_stop()
144 reg_base = dev->reg_base; in bflb_pwm_v1_set_period()
157 reg_base = dev->reg_base; in bflb_pwm_v1_channel_set_threshold()
175 reg_base = dev->reg_base; in bflb_pwm_v1_int_enable()
190 reg_base = dev->reg_base; in bflb_pwm_v1_get_intstatus()
202 reg_base = dev->reg_base; in bflb_pwm_v1_int_clear()
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A Dbflb_ir.c100 reg_base = dev->reg_base; in bflb_ir_tx_init()
201 reg_base = dev->reg_base; in bflb_ir_send()
272 reg_base = dev->reg_base; in bflb_ir_swm_send()
350 reg_base = dev->reg_base; in bflb_ir_tx_enable()
365 reg_base = dev->reg_base; in bflb_ir_txint_mask()
380 reg_base = dev->reg_base; in bflb_ir_txint_clear()
390 reg_base = dev->reg_base; in bflb_ir_get_txint_status()
400 reg_base = dev->reg_base; in bflb_ir_link_txdma()
414 reg_base = dev->reg_base; in bflb_ir_get_txfifo_cnt()
423 reg_base = dev->reg_base; in bflb_ir_txfifo_clear()
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A Dbflb_spi.c26 reg_base = dev->reg_base; in bflb_spi_init()
142 reg_base = dev->reg_base; in bflb_spi_link_txdma()
157 reg_base = dev->reg_base; in bflb_spi_link_rxdma()
170 uint32_t reg_base = dev->reg_base; in bflb_spi_poll_send() local
236 uint32_t reg_base = dev->reg_base; in bflb_spi_poll_exchange() local
406 uint32_t reg_base = dev->reg_base; in bflb_spi_txint_mask() local
420 uint32_t reg_base = dev->reg_base; in bflb_spi_rxint_mask() local
469 reg_base = dev->reg_base; in bflb_spi_get_intstatus()
480 reg_base = dev->reg_base; in bflb_spi_int_clear()
491 reg_base = dev->reg_base; in bflb_spi_isbusy()
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A Dbflb_audac.c13 uint32_t reg_base; in bflb_audac_init() local
16 reg_base = dev->reg_base; in bflb_audac_init()
124 uint32_t reg_base; in bflb_audac_volume_init() local
127 reg_base = dev->reg_base; in bflb_audac_volume_init()
165 uint32_t reg_base; in bflb_audac_link_rxdma() local
168 reg_base = dev->reg_base; in bflb_audac_link_rxdma()
186 reg_base = dev->reg_base; in bflb_audac_int_mask()
212 reg_base = dev->reg_base; in bflb_audac_int_unmask()
239 reg_base = dev->reg_base; in bflb_audac_get_intstatus()
269 reg_base = dev->reg_base; in bflb_audac_int_clear()
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A Dbflb_timer.c10 reg_base = dev->reg_base; in bflb_timer_init()
96 reg_base = dev->reg_base; in bflb_timer_deinit()
108 reg_base = dev->reg_base; in bflb_timer_start()
120 reg_base = dev->reg_base; in bflb_timer_stop()
131 reg_base = dev->reg_base; in bflb_timer_set_preloadvalue()
140 reg_base = dev->reg_base; in bflb_timer_set_compvalue()
149 reg_base = dev->reg_base; in bflb_timer_get_compvalue()
158 reg_base = dev->reg_base; in bflb_timer_get_countervalue()
168 reg_base = dev->reg_base; in bflb_timer_compint_mask()
183 reg_base = dev->reg_base; in bflb_timer_get_compint_status()
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A Dbflb_sdio2.c64 uint32_t reg_base = dev->reg_base; in bflb_sdio2_get_block_size() local
82 uint32_t reg_base = dev->reg_base; in bflb_sdio2_init() local
85 putreg16(0, reg_base + SDIO2_RD_BIT_MAP_OFFSET); in bflb_sdio2_init()
86 putreg16(0, reg_base + SDIO2_WR_BIT_MAP_OFFSET); in bflb_sdio2_init()
103 putreg8(0, reg_base + SDIO2_CARD_INT_MODE_OFFSET); in bflb_sdio2_init()
123 uint32_t reg_base = dev->reg_base; in bflb_sdio2_tx_rx_queue_init() local
151 uint32_t reg_base = dev->reg_base; in bflb_sdio2_check_host_ready() local
177 uint32_t reg_base = dev->reg_base; in bflb_sdio2_send_data() local
214 uint32_t reg_base = dev->reg_base; in bflb_sdio2_recv_data() local
272 uint32_t reg_base = 0; in bflb_sdio2_isr() local
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A Dbflb_i2s.c7 uint32_t reg_base; in bflb_i2s_init() local
11 reg_base = dev->reg_base; in bflb_i2s_init()
135 uint32_t reg_base; in bflb_i2s_deinit() local
137 reg_base = dev->reg_base; in bflb_i2s_deinit()
151 reg_base = dev->reg_base; in bflb_i2s_link_txdma()
166 reg_base = dev->reg_base; in bflb_i2s_link_rxdma()
179 uint32_t reg_base = dev->reg_base; in bflb_i2s_txint_mask() local
193 uint32_t reg_base = dev->reg_base; in bflb_i2s_rxint_mask() local
207 uint32_t reg_base = dev->reg_base; in bflb_i2s_errint_mask() local
224 reg_base = dev->reg_base; in bflb_i2s_get_intstatus()
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A Dbflb_auadc.c6 uint32_t reg_base; in bflb_auadc_init() local
9 reg_base = dev->reg_base; in bflb_auadc_init()
101 uint32_t reg_base; in bflb_auadc_adc_init() local
104 reg_base = dev->reg_base; in bflb_auadc_adc_init()
166 uint32_t reg_base; in bflb_auadc_link_rxdma() local
169 reg_base = dev->reg_base; in bflb_auadc_link_rxdma()
184 uint32_t reg_base; in bflb_auadc_int_mask() local
187 reg_base = dev->reg_base; in bflb_auadc_int_mask()
202 reg_base = dev->reg_base; in bflb_auadc_int_unmask()
218 reg_base = dev->reg_base; in bflb_auadc_get_intstatus()
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A Dbflb_sec_trng.c15 uint32_t reg_base; in bflb_trng_read() local
19 reg_base = dev->reg_base; in bflb_trng_read()
22 regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
24 putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
26 regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
28 putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
45 putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); in bflb_trng_read()
151 uint32_t reg_base; in bflb_group0_request_trng_access() local
153 reg_base = dev->reg_base; in bflb_group0_request_trng_access()
167 uint32_t reg_base; in bflb_group0_release_trng_access() local
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A Dbflb_kys.c50 uint32_t reg_base; in bflb_kys_init() local
53 reg_base = dev->reg_base; in bflb_kys_init()
102 uint32_t reg_base; in bflb_kys_enable() local
105 reg_base = dev->reg_base; in bflb_kys_enable()
117 uint32_t reg_base; in bflb_kys_disable() local
120 reg_base = dev->reg_base; in bflb_kys_disable()
136 uint32_t reg_base; in bflb_kys_int_enable() local
139 reg_base = dev->reg_base; in bflb_kys_int_enable()
168 uint32_t reg_base; in bflb_kys_get_int_status() local
171 reg_base = dev->reg_base; in bflb_kys_get_int_status()
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A Dbflb_adc.c19 reg_base = dev->reg_base; in bflb_adc_init()
156 reg_base = dev->reg_base; in bflb_adc_deinit()
204 reg_base = dev->reg_base; in bflb_adc_channel_config()
260 reg_base = dev->reg_base; in bflb_adc_start_conversion()
278 reg_base = dev->reg_base; in bflb_adc_stop_conversion()
313 reg_base = dev->reg_base; in bflb_adc_errint_mask()
338 reg_base = dev->reg_base; in bflb_adc_get_intstatus()
363 reg_base = dev->reg_base; in bflb_adc_int_clear()
443 reg_base = dev->reg_base; in bflb_adc_parse_result()
532 reg_base = dev->reg_base; in bflb_adc_tsen_init()
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A Dbflb_dac.c13 uint32_t reg_base; in bflb_dac_init() local
15 reg_base = dev->reg_base; in bflb_dac_init()
20 putreg32(regval, reg_base + GLB_GPDAC_CTRL_OFFSET); in bflb_dac_init()
60 uint32_t reg_base; in bflb_dac_channel_enable() local
62 reg_base = dev->reg_base; in bflb_dac_channel_enable()
85 uint32_t reg_base; in bflb_dac_channel_disable() local
87 reg_base = dev->reg_base; in bflb_dac_channel_disable()
106 uint32_t reg_base; in bflb_dac_link_txdma() local
109 reg_base = dev->reg_base; in bflb_dac_link_txdma()
143 uint32_t reg_base; in bflb_dac_set_value() local
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A Dbflb_emac.c93 uint32_t reg_base; in bflb_emac_bd_get_cur_active() local
94 reg_base = dev->reg_base; in bflb_emac_bd_get_cur_active()
336 uint32_t reg_base; in bflb_emac_init() local
385 reg_base = dev->reg_base; in bflb_emac_init()
449 uint32_t reg_base; in bflb_emac_deinit() local
452 reg_base = dev->reg_base; in bflb_emac_deinit()
469 uint32_t reg_base; in bflb_emac_int_enable() local
472 reg_base = dev->reg_base; in bflb_emac_int_enable()
505 reg_base = dev->reg_base; in bflb_emac_get_int_status()
573 reg_base = dev->reg_base; in bflb_emac_bd_init()
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A Dbflb_rtc.c14 uint32_t reg_base; in bflb_rtc_disable() local
17 reg_base = BFLB_RTC_BASE; in bflb_rtc_disable()
20 regval = getreg32(reg_base + HBN_CTL_OFFSET); in bflb_rtc_disable()
22 putreg32(regval, reg_base + HBN_CTL_OFFSET); in bflb_rtc_disable()
27 uint32_t reg_base; in bflb_rtc_set_time() local
31 reg_base = BFLB_RTC_BASE; in bflb_rtc_set_time()
34 regval = getreg32(reg_base + HBN_CTL_OFFSET); in bflb_rtc_set_time()
36 putreg32(regval, reg_base + HBN_CTL_OFFSET); in bflb_rtc_set_time()
40 putreg32(regval, reg_base + HBN_CTL_OFFSET); in bflb_rtc_set_time()
69 uint32_t reg_base; in bflb_rtc_get_time() local
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/bsp/cvitek/drivers/libraries/cv180x/pwm/
A Dcvi_pwm.h109 #define PWM_HLPERIOD0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD0)) argument
110 #define PWM_PERIOD0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD0)) argument
112 #define PWM_PERIOD1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD1)) argument
114 #define PWM_PERIOD2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD2)) argument
116 #define PWM_PERIOD3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD3)) argument
125 #define PWM_PWMDONE(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWMDONE)) argument
128 #define PWM_PCOUNT0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT0)) argument
129 #define PWM_PCOUNT1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT1)) argument
130 #define PWM_PCOUNT2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT2)) argument
131 #define PWM_PCOUNT3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT3)) argument
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/bsp/allwinner/libraries/sunxi-hal/hal/source/tpadc/
A Dhal_tpadc.c53 reg_val = readl(reg_base + TP_CTRL0); in sunxi_set_acqiure_time()
56 writel(reg_val, reg_base + TP_CTRL0); in sunxi_set_acqiure_time()
63 reg_val = readl(reg_base + TP_CTRL0); in sunxi_set_frequency_divider()
66 writel(reg_val, reg_base + TP_CTRL0); in sunxi_set_frequency_divider()
73 reg_val = readl(reg_base + TP_CTRL0); in sunxi_set_clk_divider()
76 writel(reg_val, reg_base + TP_CTRL0); in sunxi_set_clk_divider()
83 reg_val = readl(reg_base + TP_CTRL0); in sunxi_select_delay_mode()
105 sunxi_set_dealy_time(reg_base, 0xf); in sunxi_clk_init()
378 return readl(reg_base + TP_DATA); in hal_tpadc_data_read()
512 sunxi_clk_init(tpadc->reg_base); in hal_tpadc_init()
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/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/
A Dbflb_sf_ctrl.c125 uint32_t reg_base = 0; in bflb_sf_ctrl_enable() local
264 uint32_t reg_base = 0; in bflb_sf_ctrl_bank2_enable() local
338 uint32_t reg_base = 0; in bflb_sf_ctrl_sbus2_hold_sram() local
360 uint32_t reg_base = 0; in bflb_sf_ctrl_sbus2_release_sram() local
382 uint32_t reg_base = 0; in bflb_sf_ctrl_is_sbus2_enable() local
410 uint32_t reg_base = 0; in bflb_sf_ctrl_sbus2_replace() local
452 uint32_t reg_base = 0; in bflb_sf_ctrl_sbus2_revoke_replace() local
484 uint32_t reg_base = 0; in bflb_sf_ctrl_sbus2_set_delay() local
519 uint32_t reg_base = 0; in bflb_sf_ctrl_remap_set() local
551 uint32_t reg_base = 0; in bflb_sf_ctrl_32bits_addr_en() local
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/bsp/allwinner/libraries/sunxi-hal/hal/source/gpadc/
A Dhal_gpadc.c238 static void gpadc_calibration_enable(uint32_t reg_base) in gpadc_calibration_enable() argument
246 static void gpadc_mode_select(uint32_t reg_base, in gpadc_mode_select() argument
258 static void gpadc_enable(uint32_t reg_base) in gpadc_enable() argument
268 static void gpadc_disable(uint32_t reg_base) in gpadc_disable() argument
345 reg_val = gpadc_channel_irq_status(gpadc->reg_base); in gpadc_handler()
346 gpadc_channel_clear_irq(gpadc->reg_base, reg_val); in gpadc_handler()
356 data = gpadc_read_data(gpadc->reg_base, i); in gpadc_handler()
433 gpadc->reg_base = GPADC_BASE; in hal_gpadc_setup()
476 gpadc_calibration_enable(gpadc->reg_base); in hal_gpadc_init()
477 gpadc_mode_select(gpadc->reg_base, gpadc->mode); in hal_gpadc_init()
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