Home
last modified time | relevance | path

Searched refs:reg_val (Results 1 – 25 of 65) sorted by relevance

123

/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/
A Dbflb_emac.c337 uint32_t reg_val; in bflb_emac_init() local
450 uint32_t reg_val; in bflb_emac_deinit() local
589 uint32_t reg_val; in bflb_emac_phy_reg_read() local
628 uint32_t reg_val; in bflb_emac_phy_reg_write() local
669 uint32_t reg_val; in bflb_emac_feature_control() local
798 uint32_t reg_val; in bflb_emac_stop() local
814 uint32_t reg_val; in bflb_emac_start() local
829 uint32_t reg_val; in bflb_emac_start_tx() local
844 uint32_t reg_val; in bflb_emac_stop_tx() local
859 uint32_t reg_val; in bflb_emac_start_rx() local
[all …]
A Dbflb_kys.c51 uint32_t reg_val; in bflb_kys_init() local
56 reg_val &= ~(KYS_KS_EN_MASK); in bflb_kys_init()
62 reg_val &= ~(KYS_KS_INT_EN_MASK); in bflb_kys_init()
64 reg_val &= ~(KYS_KS_DONE_INT_EN_MASK | in bflb_kys_init()
75 reg_val &= ~(KYS_COL_NUM_MASK | in bflb_kys_init()
103 uint32_t reg_val; in bflb_kys_enable() local
107 reg_val |= (0x1 << KYS_KS_EN_SHIFT); in bflb_kys_enable()
118 uint32_t reg_val; in bflb_kys_disable() local
123 reg_val &= ~(KYS_KS_EN_MASK); in bflb_kys_disable()
191 uint32_t reg_val; in bflb_kys_get_fifo_info() local
[all …]
A Dbflb_ef_ctrl.c60 uint32_t reg_val; in bflb_ef_ctrl_switch_ahb_clk_r0() local
99 uint32_t reg_val; in bflb_ef_ctrl_switch_ahb_clk_r1() local
146 uint32_t reg_val; in bflb_ef_ctrl_program_efuse_r0() local
208 uint32_t reg_val; in bflb_ef_ctrl_program_efuse_r1() local
326 uint32_t reg_val; in bflb_ef_ctrl_load_efuse_r0() local
399 uint32_t reg_val; in bflb_ef_ctrl_load_efuse_r1() local
481 uint32_t reg_val; in bflb_ef_ctrl_busy() local
502 uint32_t reg_val; in bflb_ef_ctrl_autoload_done() local
694 uint32_t reg_val; in bflb_ef_ctrl_read_common_trim() local
753 reg_val = reg_val >> (trim_list[i].value_addr % 32); in bflb_ef_ctrl_read_common_trim()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/tpadc/
A Dhal_tpadc.c28 uint32_t reg_val; in sunxi_flush_fifo() local
31 reg_val = SET_BITS(TP_FIFO_FLUSH, TP_FIFO_FLUSH_WIDTH,reg_val, 0x1); in sunxi_flush_fifo()
38 uint32_t reg_val; in sunxi_clear_fifo_status() local
54 reg_val = SET_BITS(TACQ, TACQ_WIDTH, reg_val, val); in sunxi_set_acqiure_time()
64 reg_val = SET_BITS(FS_DIV, FS_DIV_WIDTH, reg_val, val); in sunxi_set_frequency_divider()
152 reg_val = SET_BITS(TP_EN, TP_EN_WIDTH, reg_val, val); in sunxi_tpadc_enable()
172 reg_val = SET_BITS(PRE_MEA, PRE_MEA_WIDTH, reg_val, val); in sunxi_set_pressure_thresholed()
222 reg_val = SET_BITS(FILTER_EN, FILTER_EN_WIDTH, reg_val, 0x1); in sunxi_filter_enable()
322 u32 reg_val; in sunxi_tpadc_ch_select() local
349 u32 reg_val; in sunxi_tpadc_ch_deselect() local
[all …]
/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8978/
A Dhpm_wm8978.c186 reg_val = 0; in wm8978_cfg_audio_channel()
207 reg_val = 0; in wm8978_cfg_audio_channel()
233 reg_val = 0; in wm8978_cfg_audio_channel()
249 reg_val = 0; in wm8978_cfg_audio_channel()
258 reg_val = 0; in wm8978_cfg_audio_channel()
271 reg_val = 0xFF; in wm8978_cfg_audio_channel()
278 reg_val = 0; in wm8978_cfg_audio_channel()
288 reg_val = 0; in wm8978_cfg_audio_channel()
302 reg_val = 0; in wm8978_cfg_audio_channel()
315 reg_val = 0; in wm8978_cfg_audio_channel()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/ledc/
A Dhal_ledc.c95 reg_val |= (n << 16); in ledc_set_reset_ns()
172 reg_val &= ~0x3F; in ledc_set_t0l_ns()
173 reg_val |= n; in ledc_set_t0l_ns()
247 reg_val &= ~0x3FF; in ledc_set_length()
278 reg_val |= val; in ledc_set_output_mode()
287 reg_val &= ~mask; in ledc_disable_irq()
296 reg_val |= mask; in ledc_enable_irq()
304 reg_val |= 1 << 5; in ledc_set_dma_mode()
321 reg_val |= 0x1F; in ledc_clear_all_irq()
335 reg_val |= 1 << 1; in ledc_soft_reset()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/lowlevel_v2x/
A Dde_clock.c73 u32 reg_val; in de_clk_set_div() local
80 reg_val = in de_clk_set_div()
93 reg_val = in de_clk_set_div()
111 u32 reg_val; in __de_clk_enable() local
172 u32 reg_val; in __de_clk_disable() local
180 reg_val = in __de_clk_disable()
183 reg_val = in __de_clk_disable()
192 reg_val = in __de_clk_disable()
194 reg_val = in __de_clk_disable()
203 reg_val = in __de_clk_disable()
[all …]
A Dde_eink.c108 unsigned reg_val = 0; in eink_irq_query() local
111 dec_irq = reg_val&0x1; in eink_irq_query()
112 idx_irq = reg_val&0x2; in eink_irq_query()
128 unsigned reg_val = 0; in eink_irq_query_index() local
131 idx_irq = reg_val&0x2; in eink_irq_query_index()
197 unsigned int reg_val; in eink_index_finish() local
200 if (reg_val == 0x2) in eink_index_finish()
208 unsigned int reg_val; in eink_get_updata_area() local
211 info->x_top = reg_val & 0xfff; in eink_get_updata_area()
215 info->x_bottom = reg_val & 0xfff; in eink_get_updata_area()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/gpadc/
A Dhal_gpadc.c95 uint32_t reg_val; in gpadc_channel_select() local
106 uint32_t reg_val; in gpadc_channel_deselect() local
117 uint32_t reg_val; in gpadc_compare_select() local
128 uint32_t reg_val; in gpadc_compare_deselect() local
139 uint32_t reg_val; in gpadc_channel_enable_lowirq() local
149 uint32_t reg_val; in gpadc_channel_disable_lowirq() local
180 uint32_t reg_val; in gpadc_channel_enable_highirq() local
191 uint32_t reg_val; in gpadc_channel_disable_highirq() local
240 uint32_t reg_val; in gpadc_calibration_enable() local
249 uint32_t reg_val; in gpadc_mode_select() local
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/cir/
A Dhal_cir.c110 int reg_val; in sunxi_cir_mode_enable() local
128 int reg_val; in sunxi_cir_mode_config() local
144 int reg_val = 0; in sunxi_cir_sample_clock_select() local
165 int reg_val = 0; in sunxi_cir_sample_noise_threshold() local
181 int reg_val = 0; in sunxi_cir_sample_idle_threshold() local
197 int reg_val = 0; in sunxi_cir_sample_active_threshold() local
213 int reg_val = 0; in sunxi_cir_sample_active_thrctrl() local
231 int reg_val = 0; in sunxi_cir_fifo_level() local
238 reg_val &= ~RAL; in sunxi_cir_fifo_level()
247 int reg_val = 0; in sunxi_cir_irq_enable() local
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/lradc/
A Dhal_lradc.c47 uint32_t reg_val = 0; in lradc_ctrl_set() local
49 reg_val = hal_readl(base_addr + LRADC_CTRL_REG); in lradc_ctrl_set()
50 reg_val |= ctrl_para; in lradc_ctrl_set()
51 hal_writel(reg_val, base_addr + LRADC_CTRL_REG); in lradc_ctrl_set()
56 uint32_t reg_val = 0; in lradc_ctrl_reset() local
59 reg_val &= ~ctrl_para; in lradc_ctrl_reset()
65 uint32_t reg_val = 0; in lradc_irq_set() local
68 reg_val |= irq_para; in lradc_irq_set()
74 uint32_t reg_val = 0; in lradc_irq_reset() local
77 reg_val &= ~irq_para; in lradc_irq_reset()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/pwm/
A Dhal_pwm.c93 uint32_t reg_val; in hal_pwm_clk_src_set() local
99 reg_val = SET_REG_VAL(reg_val, PWM_CLK_SRC_SHIFT, PWM_CLK_SRC_WIDTH, clk_src); in hal_pwm_clk_src_set()
111 uint32_t reg_val; in hal_pwm_clk_div_m() local
117 reg_val = SET_REG_VAL(reg_val, PWM_DIV_M_SHIFT, PWM_DIV_M_WIDTH, div_m); in hal_pwm_clk_div_m()
125 uint32_t reg_val; in hal_pwm_prescal_set() local
131 reg_val = SET_REG_VAL(reg_val, PWM_PRESCAL_SHIFT, PWM_PRESCAL_WIDTH, prescal); in hal_pwm_prescal_set()
141 uint32_t reg_val; in hal_pwm_set_active_cycles() local
155 uint32_t reg_val; in hal_pwm_set_period_cycles() local
199 uint32_t reg_val; in hal_pwm_enable_clk_gating() local
212 uint32_t reg_val; in hal_pwm_enable_controller() local
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/regulator/
A Daxp.c34 *reg_val = 0; in voltage2val()
39 *reg_val += range->min_sel; in voltage2val()
57 if (!(reg_val <= range->max_sel && reg_val >= range->min_sel)) in val2voltage()
107 u8 reg_val = 0; in axp_regulator_enable() local
109 reg_val = info->enable_val; in axp_regulator_enable()
110 if (!reg_val) in axp_regulator_enable()
111 reg_val = info->enable_mask; in axp_regulator_enable()
122 u8 reg_val = 0; in axp_regulator_disable() local
124 reg_val = info->disable_val; in axp_regulator_disable()
125 if (!reg_val) in axp_regulator_disable()
[all …]
A Daxp_twi.c21 int hal_axp_byte_read(struct regulator_dev *rdev, u8 reg, u8 *reg_val) in hal_axp_byte_read() argument
26 ret = hal_twi_read(port, reg, reg_val, 1); in hal_axp_byte_read()
33 int hal_axp_byte_write(struct regulator_dev *rdev, u8 reg, u8 reg_val) in hal_axp_byte_write() argument
41 buf[1] = reg_val; in hal_axp_byte_write()
52 u8 reg_val = 0; in hal_axp_byte_update() local
55 ret = hal_axp_byte_read(rdev, reg, &reg_val); in hal_axp_byte_update()
59 if ((reg_val & mask) != val) { in hal_axp_byte_update()
60 reg_val = (reg_val & ~mask) | (val & mask); in hal_axp_byte_update()
61 ret = hal_axp_byte_write(rdev, reg, reg_val); in hal_axp_byte_update()
/bsp/allwinner/libraries/sunxi-hal/hal/source/twi/
A Dhal_twi.c243 reg_val |= mask; in twi_enable()
264 reg_val >>= 5; in twi_get_start()
283 reg_val >>= 4; in twi_get_stop()
329 reg_val |= efr; in twi_set_efr()
659 reg_val |= val; in twi_set_rx_trig_level()
671 reg_val |= val; in twi_set_packet_addr_byte()
683 reg_val |= val; in twi_set_packet_data_byte()
697 reg_val |= val;
710 reg_val |= val; in twi_set_packet_cnt()
811 return reg_val; in twi_query_txfifo()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/spi/
A Dhal_spi.c287 reg_val |= SPI_GC_EN; in spi_enable_bus()
350 reg_val |= bitmap; in spi_enable_irq()
360 reg_val &= ~bitmap; in spi_disable_irq()
370 reg_val |= bitmap; in spi_enable_dma_irq()
380 reg_val &= ~bitmap; in spi_disable_dma_irq()
406 uint32_t reg_val = in spi_query_txfifo() local
410 return reg_val; in spi_query_txfifo()
416 uint32_t reg_val = in spi_query_rxfifo() local
420 return reg_val; in spi_query_rxfifo()
459 uint32_t reg_val; in spi_set_bc_tc_stc() local
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/usb/host/
A Dehci-sunxi.c373 u32 reg_val = 0; in ehci_disable_periodic_schedule() local
376 reg_val &= ~(0x1<<4); in ehci_disable_periodic_schedule()
386 reg_val &= ~(0x1<<5); in ehci_disable_async_schedule()
402 reg_val &= (~0x1); in ehci_test_stop()
409 u32 reg_val = 0; in ehci_test_reset() local
412 reg_val |= (0x1<<1); in ehci_test_reset()
423 reg_val &= (0x1<<1); in ehci_test_reset_complete()
425 return !reg_val; in ehci_test_reset_complete()
433 reg_val |= 0x1; in ehci_start()
443 reg_val &= 0x1; in ehci_is_halt()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/efuse/
A Defuse.c116 uint reg_val; in _efuse_reg_read_key() local
124 reg_val &= ~((0x1ff<<16)|0x3); in _efuse_reg_read_key()
125 reg_val |= key_index<<16; in _efuse_reg_read_key()
127 reg_val &= ~((0xff<<8)|0x3); in _efuse_reg_read_key()
128 reg_val |= (SID_OP_LOCK<<8) | 0x2; in _efuse_reg_read_key()
138 return reg_val; in _efuse_reg_read_key()
144 uint reg_val; in _efuse_program_key() local
155 reg_val &= ~((0x1ff<<16)|0x3); in _efuse_program_key()
156 reg_val |= key_index<<16; in _efuse_program_key()
158 reg_val &= ~((0xff<<8)|0x3); in _efuse_program_key()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/sound/platform/
A Dsunxi-mad.c359 unsigned int reg_val = 0; in sunxi_mad_sram_chan_params() local
476 unsigned int reg_val = 0; in sunxi_mad_lpsd_chan_enable() local
499 unsigned int reg_val = 0; in sunxi_mad_irq_status_clear() local
515 unsigned int reg_val = 0; in sunxi_lpsd_irq_status_clear() local
679 u32 reg_val = 0; in sunxi_mad_enable() local
689 reg_val |= ~(0x1 << MAD_RUN); in sunxi_mad_enable()
690 mad_is_worked = ~reg_val; in sunxi_mad_enable()
800 unsigned int reg_val[4] = {0}; in sunxi_mad_show_all_regs() local
811 reg_val[0], reg_val[1], reg_val[2], reg_val[3]); in sunxi_mad_show_all_regs()
932 unsigned int reg_val = 0; in sunxi_mad_work_resume() local
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_pixelmux_drv.c13 uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_RGB_SEL_MASK) | in pixelmux_rgb_data_source_enable() local
15 HPM_PIXEL_MUX->PIXMUX = reg_val; in pixelmux_rgb_data_source_enable()
25 uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_GWC1_SEL_MASK) | in pixelmux_gwc1_data_source_enable() local
27 HPM_PIXEL_MUX->PIXMUX = reg_val; in pixelmux_gwc1_data_source_enable()
39 HPM_PIXEL_MUX->PIXMUX = reg_val; in pixelmux_gwc0_data_source_enable()
51 HPM_PIXEL_MUX->PIXMUX = reg_val; in pixelmux_lvb_di1_data_source_enable()
63 HPM_PIXEL_MUX->PIXMUX = reg_val; in pixelmux_lvb_di0_data_source_enable()
75 HPM_PIXEL_MUX->PIXMUX = reg_val; in pixelmux_mipi_dsi1_data_source_enable()
87 HPM_PIXEL_MUX->PIXMUX = reg_val; in pixelmux_mipi_dsi0_data_source_enable()
113 HPM_PIXEL_MUX->PIXMUX = reg_val; in pixelmux_cam1_data_source_enable()
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/ce/
A Dhal_ce.c70 uint32_t reg_val; in hal_ce_clock_init()
72 reg_val = readl(CCMU_CE_CLK_REG); in hal_ce_clock_init()
82 writel(reg_val, CCMU_CE_CLK_REG); in hal_ce_clock_init()
93 writel(reg_val, CCMU_CE_CLK_REG); in hal_ce_clock_init()
96 reg_val = readl(CCMU_CE_BGR_REG); in hal_ce_clock_init()
98 writel(reg_val, CCMU_CE_BGR_REG); in hal_ce_clock_init()
101 reg_val = readl(CCMU_CE_BGR_REG); in hal_ce_clock_init()
102 reg_val |= CE_DEASSERT << CE_RST_BIT; in hal_ce_clock_init()
103 writel(reg_val, CCMU_CE_BGR_REG); in hal_ce_clock_init()
106 reg_val = readl(MBUS_MAT_CLK_GATING_REG); in hal_ce_clock_init()
[all …]
/bsp/cvitek/drivers/
A Ddrv_gpio.c88 rt_uint32_t reg_val; in dwapb_pin_mode() local
94 reg_val = dwapb_read32(base_addr + GPIO_SWPORTA_DDR); in dwapb_pin_mode()
98 reg_val |= BIT(bit); in dwapb_pin_mode()
101 reg_val &= ~BIT(bit); in dwapb_pin_mode()
112 rt_uint32_t reg_val; in dwapb_pin_write() local
118 reg_val = dwapb_read32(base_addr + GPIO_SWPORTA_DR); in dwapb_pin_write()
119 reg_val = (value ? (reg_val | BIT(bit)) : (reg_val & (~BIT(bit)))); in dwapb_pin_write()
120 dwapb_write32(base_addr + GPIO_SWPORTA_DR, reg_val); in dwapb_pin_write()
133 return ((reg_val >> (bit)) & 1); in dwapb_pin_read()
248 reg_val = (enabled ? (reg_val | BIT(bit)) : (reg_val & (~BIT(bit)))); in dwapb_pin_irq_enable()
[all …]
/bsp/k230/drivers/interdrv/ts/
A Ddrv_ts.c70 uint32_t reg_val; in tsensor_start() local
75 reg_val = readl(ts_base_addr + REG_TSENW_OFFSET); in tsensor_start()
78 reg_val |= (1 << TSENW_TS_CONV_MODE_POS); in tsensor_start()
80 reg_val &= ~(1 << TSENW_TS_CONV_MODE_POS); in tsensor_start()
82 reg_val |= (1 << TSENW_TS_EN_POS); in tsensor_start()
84 writel(reg_val, ts_base_addr + REG_TSENW_OFFSET); in tsensor_start()
95 reg_val &= ~(1 << TSENW_TS_EN_POS); in tsensor_stop()
96 writel(reg_val, ts_base_addr + REG_TSENW_OFFSET); in tsensor_stop()
148 reg_val &= ~(0xF << TSENW_TS_TRIM_POS); in tsensor_init()
149 reg_val |= (ts_trim << TSENW_TS_TRIM_POS); in tsensor_init()
[all …]
/bsp/ck802/drivers/
A Dpinmux.c85 unsigned int reg_val = 0; in pin_mux() local
124 reg_val = (0x3 << (offset * 2)); in pin_mux()
127 val &= ~(reg_val); in pin_mux()
142 reg_val = (0x3 << (offset * 2)); in pin_mux()
145 val &= ~(reg_val); in pin_mux()
151 reg_val = (0x3 << (offset * 2)); in pin_mux()
154 val &= ~(reg_val); in pin_mux()
/bsp/allwinner/libraries/sunxi-hal/hal/test/twi/
A Dtest_twi.c50 char reg_addr, reg_val = 0, rw = TEST_READ; in cmd_test_twi() local
78 reg_val = strtol(argv[5], NULL, 0); in cmd_test_twi()
90 hal_twi_read(port, reg_addr, &reg_val, 1); in cmd_test_twi()
91 hal_log_info("reg_val: 0x%x", reg_val); in cmd_test_twi()
101 buf[1] = reg_val; in cmd_test_twi()

Completed in 70 milliseconds

123