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Searched refs:round_rate (Results 1 – 15 of 15) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/
A Dclk_periph.c412 u32 i = 0, round_rate = 0; in sunxi_clk_periph_round_rate() local
420 round_rate = (prate + rate / 2 - 1); in sunxi_clk_periph_round_rate()
426 do_div(round_rate, rate); in sunxi_clk_periph_round_rate()
427 div = round_rate; in sunxi_clk_periph_round_rate()
433 round_rate = prate; in sunxi_clk_periph_round_rate()
452 do_div(round_rate, (factor_m + 1) * (1 << factor_n)); in sunxi_clk_periph_round_rate()
463 do_div(round_rate, (factor_m + 1) * (1 << factor_n)); in sunxi_clk_periph_round_rate()
472 do_div(round_rate, (factor_m + 1) * (1 << factor_n)); in sunxi_clk_periph_round_rate()
475 CCMU_DBG("parent rate %dHZ, target rate %dHZ, round rate %dHZ\n", prate, rate, round_rate); in sunxi_clk_periph_round_rate()
477 return round_rate; in sunxi_clk_periph_round_rate()
A Dclk.c414 u32 i, parent_rate = 0, round_rate = 0; in sunxi_clk_round_rate() local
440 round_rate = sunxi_clk_factors_round_rate(factor_clk, rate); in sunxi_clk_round_rate()
441 if (round_rate == 0) in sunxi_clk_round_rate()
446 *prate = round_rate; in sunxi_clk_round_rate()
453 round_rate = sunxi_clk_periph_round_rate(periph_clk, rate, parent_rate); in sunxi_clk_round_rate()
454 if (round_rate == 0) in sunxi_clk_round_rate()
459 *prate = round_rate; in sunxi_clk_round_rate()
651 u32 i = 0, parent_rate = 0, round_rate = 0, check_rate = 0; in sunxi_periph_bus_clk_init() local
693 CCMU_DBG("get round rate %dHZ\n", round_rate); in sunxi_periph_bus_clk_init()
704 CCMU_DBG("set new rate %dHZ\n", round_rate); in sunxi_periph_bus_clk_init()
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/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/
A Dhal_clk.c76 u32 round_rate = 0; in hal_clk_round_rate() local
79 clk_round_rate(clk, rate, &round_rate); in hal_clk_round_rate()
81 return round_rate; in hal_clk_round_rate()
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/
A Dclk.c175 hal_clk_status_t clk_round_rate(struct clk *clk, u32 rate, u32 *round_rate) in clk_round_rate() argument
179 round_rate = 0; in clk_round_rate()
183 *round_rate = clk_core_round_rate(clk->core, rate); in clk_round_rate()
A Dclk-fixed-factor.c67 .round_rate = clk_factor_round_rate,
A Dccu_gate.c137 .round_rate = ccu_gate_round_rate,
A Dccu.c198 else if (core->ops->round_rate) in clk_core_determine_round_nolock()
200 rate = core->ops->round_rate(core->hw, req->rate, in clk_core_determine_round_nolock()
242 return core->ops->determine_rate || core->ops->round_rate; in clk_core_can_round()
A Dccu_nk.c174 .round_rate = ccu_nk_round_rate,
A Dclk-divider.c576 .round_rate = clk_divider_round_rate,
583 .round_rate = clk_divider_round_rate,
A Dccu_nkmp.c272 .round_rate = ccu_nkmp_round_rate,
A Dccu_nm.c279 .round_rate = ccu_nm_round_rate,
A Dccu.h310 long (*round_rate)(struct clk_hw *hw, unsigned long rate, member
/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/
A Ddisp_hdmi.c131 unsigned long rate = 0, round_rate = 0; in hdmi_clk_config() local
154 round_rate = clk_round_rate(hdmip->clk, rate); in hdmi_clk_config()
155 rate_diff = (long)(round_rate - rate); in hdmi_clk_config()
/bsp/rockchip/rk3500/driver/clk/
A Dclk-rk3588.c3121 .round_rate = rk3588_clk_round_rate,
A Dclk-rk3568.c4621 .round_rate = rk3568_clk_round_rate,

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