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Searched refs:rt_ioremap (Results 1 – 25 of 72) sorted by relevance

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/bsp/raspberry-pi/raspi4-64/drivers/
A Dboard.c117 gpio_base_addr = (size_t)rt_ioremap((void*)GPIO_BASE_ADDR, 0x1000); in rt_hw_board_init()
120 pactl_cs_base = (size_t)rt_ioremap((void*)PACTL_CS_ADDR, 0x1000); in rt_hw_board_init()
123 stimer_base_addr = (size_t)rt_ioremap((void*)STIMER_BASE, 0x1000); in rt_hw_board_init()
126 mmc2_base_addr = (size_t)rt_ioremap((void*)MMC2_BASE_ADDR, 0x1000); in rt_hw_board_init()
129 videocore_mbox = (size_t)rt_ioremap((void*)VIDEOCORE_MBOX, 0x1000); in rt_hw_board_init()
135 wdt_base_addr = (size_t)rt_ioremap((void*)WDT_BASE, 0x1000); in rt_hw_board_init()
138 mac_reg_base_addr = (void *)rt_ioremap((void*)MAC_REG, 0x80000); in rt_hw_board_init()
183 release_addr = rt_ioremap((void *)cpu_release_paddr[i], sizeof(cpu_release_paddr[0])); in rt_hw_secondary_cpu_up()
A Ddrv_uart.c336 uart0_addr = (size_t)rt_ioremap((void*)UART0_BASE, 0x1000); in rt_hw_uart_init()
357 uart1->hw_base = (size_t)rt_ioremap((void*)AUX_BASE, 0x1000); in rt_hw_uart_init()
373 uart3_addr = (size_t)rt_ioremap((void*)UART3_BASE, 0x1000); in rt_hw_uart_init()
390 uart4_addr = (size_t)rt_ioremap((void*)UART4_BASE, 0x1000); in rt_hw_uart_init()
407 uart5_addr = (size_t)rt_ioremap((void*)UART5_BASE, 0x1000); in rt_hw_uart_init()
/bsp/phytium/libraries/common/
A Dfearly_uart.c52 config.msg.regfile = (uintptr)rt_ioremap((void *)config.msg.regfile, 0x1000); in FEarlyUartProbe()
53 config.msg.shmem = (uintptr)rt_ioremap((void *)config.msg.shmem, 0x1000); in FEarlyUartProbe()
86 config.base_address = (uintptr)rt_ioremap((void *)config.base_address, 0x2000); in FEarlyUartProbe()
A Dphytium_interrupt.c106 gic_dist_base = (rt_uint64_t)rt_ioremap((void *)platform_get_gic_dist_base(), 0x40000); in phytium_interrupt_init()
107 gic_cpu_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_cpu_base(), 0x1000); in phytium_interrupt_init()
/bsp/qemu-vexpress-a9/drivers/
A Ddrv_timer.c78 sys_ctrl = (void*)rt_ioremap((void*)REALVIEW_SCTL_BASE, 0x1000); in rt_hw_timer_init()
79 timer_hw_base = (void*)rt_ioremap((void*)REALVIEW_TIMER2_3_BASE, 0x1000); in rt_hw_timer_init()
112 timer01_hw_base = (void*)rt_ioremap((void*)TIMER01_HW_BASE_PHY, 0x1000); in timer_init()
130 timer23_hw_base = (void*)rt_ioremap((void*)TIMER23_HW_BASE_PHY, 0x1000); in timer_init()
/bsp/xuantie/virt64/c906/libcpu/
A Dplic.c26 #define rt_ioremap(addr, ...) (addr) macro
131 plic_base = (size_t)rt_ioremap((void *)plic_base, 64 * 1024 * 1024); in plic_init()
/bsp/nxp/imx/imx6ull-smart/drivers/
A Ddrv_timer.c100 CCM_CLPCR = rt_ioremap((void*)0x20C4054, 4); in imx6ull_enable_clk_in_waitmode()
116 …struct sctr_regs *sctr = (struct sctr_regs *)rt_ioremap((void*)SCTR_BASE_ADDR, sizeof(struct sctr_… in system_counter_init()
A Ddrv_sdio.c110 *((volatile uint32_t *)rt_ioremap((void*)muxRegister, 0x4)) = in _IOMUXC_SetPinMux()
115 …*((volatile uint32_t *)rt_ioremap((void*)inputRegister, 0x4)) = IOMUXC_SELECT_INPUT_DAISY(inputDai… in _IOMUXC_SetPinMux()
144 *((volatile uint32_t *)rt_ioremap((void*)configRegister, 0x4)) = configValue; in _IOMUXC_SetPinConfig()
615 mmcsd1->usdhc_host.base = (USDHC_Type *)rt_ioremap((void*)USDHC1_BASE, 0x1000); in imxrt_mci_init()
657 mmcsd2->usdhc_host.base = (USDHC_Type *)rt_ioremap((void*)USDHC2_BASE, 0x1000); in imxrt_mci_init()
A Ddrv_common.c23 return rt_ioremap((void *)paddr, sizeof(sizeof(rt_uint32_t))); in imx6ull_get_periph_vaddr()
/bsp/phytium/libraries/drivers/
A Ddrv_pwm.c42 config.lsd_config_addr = (uintptr)rt_ioremap((void *)config.lsd_config_addr, 0x100); in drv_pwm_config()
43 config.pwm_base_addr = (uintptr)rt_ioremap((void *)config.pwm_base_addr, 0x1000); in drv_pwm_config()
44 config.db_base_addr = (uintptr)rt_ioremap((void *)config.db_base_addr, 0x100); in drv_pwm_config()
A Ddrv_spi_msg.c153 input_cfg.spi_msg.regfile = (uintptr)rt_ioremap((void *)input_cfg.spi_msg.regfile, 0x1000); in spi_init()
154 input_cfg.spi_msg.shmem = (uintptr)rt_ioremap((void *)input_cfg.spi_msg.shmem, 0x1000); in spi_init()
A Ddrv_gpio.c67 input_cfg.base_addr = (uintptr)rt_ioremap((void *)input_cfg.base_addr, 0x1000); in drv_pin_mode()
116 map->base_addr = (uintptr)rt_ioremap((void *)map->base_addr, 0x1000); in drv_pin_attach_irq()
A Ddrv_usart_msg.c66 config.msg.regfile = (uintptr)rt_ioremap((void *)config.msg.regfile, 0x1000); in uart_msg_configure()
67 config.msg.shmem = (uintptr)rt_ioremap((void *)config.msg.shmem, 0x1000); in uart_msg_configure()
A Ddrv_i2c_msg.c56 input_cfg.msg.shmem = (uintptr)rt_ioremap((void *)input_cfg.msg.shmem, 0x1000); in i2c_msg_config()
57 input_cfg.msg.regfile= (uintptr)rt_ioremap((void *)input_cfg.msg.regfile, 0x1000); in i2c_msg_config()
A Ddrv_qspi.c45 pconfig.base_addr = (uintptr)rt_ioremap((void *)pconfig.base_addr, 0x1000); in FQspiInit()
321 addr = (uintptr)rt_ioremap((void *)addr, len); in phytium_qspi_xfer()
353 addr = (uintptr)rt_ioremap((void *)addr, len); in phytium_qspi_xfer()
A Ddrv_i2c.c60 input_cfg.base_addr = (uintptr)rt_ioremap((void *)input_cfg.base_addr, 0x1000); in i2c_config()
98 …mio_handle.config.func_base_addr = (uintptr)rt_ioremap((void *)mio_handle.config.func_base_addr, 0… in i2c_mio_config()
99 …mio_handle.config.mio_base_addr = (uintptr)rt_ioremap((void *)mio_handle.config.mio_base_addr, 0x2… in i2c_mio_config()
/bsp/cvitek/drivers/
A Ddrv_ioremap.h19 #define DRV_IOREMAP(addr, size) rt_ioremap(addr, size)
/bsp/ultrarisc/arch/ur-cp100/
A Dplic.c31 #define rt_ioremap(addr, ...) (addr) macro
139 plic_base = (size_t)rt_ioremap((void *)plic_base, 64 * 1024 * 1024); in plic_init()
/bsp/k230/drivers/interdrv/sysctl/sysctl_boot/
A Dsysctl_boot.c88 sysctl_boot = rt_ioremap((void*)BOOT_BASE_ADDR, BOOT_IO_SIZE); in rt_hw_sysctl_boot_init()
/bsp/raspberry-pi/raspi-dm2.0/drivers/sdhci/src/
A Dsdhci_dma.c33 v = rt_ioremap((void *)*dma_handle, size); in dma_alloc_coherent()
/bsp/xuantie/virt64/c906/board/
A Ddrv_virtio.c47 mmio_base = (rt_ubase_t)rt_ioremap((void *)mmio_base, VIRTIO_MMIO_SIZE * VIRTIO_MAX_NR); in rt_virtio_devices_init()
/bsp/qemu-virt64-aarch64/drivers/
A Ddrv_virtio.c65 mmio_base = (rt_ubase_t)rt_ioremap((void *)mmio_base, VIRTIO_MMIO_SIZE * VIRTIO_MAX_NR); in rt_virtio_devices_init()
/bsp/qemu-virt64-riscv/driver/
A Ddrv_virtio.c70 mmio_base = (rt_ubase_t)rt_ioremap((void *)mmio_base, VIRTIO_MMIO_SIZE * VIRTIO_MAX_NR); in rt_virtio_devices_init()
/bsp/phytium/board/
A Dphytium_cpu.h63 uintptr_t redis_base_virtual = (uintptr_t)rt_ioremap((void *)redis_base, GICV3_RD_OFFSET); in platform_get_gic_redist_base()
/bsp/k230/drivers/interdrv/hardlock/
A Ddrv_hardlock.c100 hard->hw_base = 0xA0 + rt_ioremap((void *)MAILBOX_BASE_ADDR, MAILBOX_IO_SIZE); in rt_hw_hardlock_init()

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