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Searched refs:saddr (Results 1 – 12 of 12) sorted by relevance

/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/
A Dhal_udma_qspi_reg_defs.h50 __IO uint32_t saddr : 12; member
80 __IO uint32_t saddr : 12; member
110 __IO uint32_t saddr : 32; member
A Dhal_udma_i2cm_reg_defs.h50 __IO uint32_t saddr : 12; member
79 __IO uint32_t saddr : 12; member
A Dhal_udma_uart_reg_defs.h50 __IO uint32_t saddr : 12; member
79 __IO uint32_t saddr : 12; member
A Dhal_udma_sdio_reg_defs.h50 __IO uint32_t saddr : 32; // 21 localparam L2_AWIDTH_NOAL = L2_ADDR_WIDTH + 2; member
80 __IO uint32_t saddr : 12; member
A Dhal_udma_cam_reg_defs.h50 __IO uint32_t saddr : 32; member
A Dudma_camera_reg_defs.h50 __IO uint32_t saddr : 32; member
A Dhal_udma_core_periph.h31 volatile uint32_t saddr; /**< RX/TX/CMD Channel uDMA transfer address of associated buffer */ member
/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/
A Dald_qspi.h237 uint32_t saddr; /**< Flash start address, commence write operation*/ member
242 uint32_t saddr; /**< FLASH start address, commence read operation*/ member
515 ald_status_t ald_qspi_indac_transmit_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, ui…
516 ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, …
517 ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uin…
518 ald_status_t ald_qspi_indac_read_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint1…
/bsp/upd70f3454/drivers/
A Dcstartup.asm134 ; Initialize the saddr base pointers. ;
752 ; Define the base of the short addressing (saddr) data. ;
754 ; This empty segment should be places in front of the saddr ;
/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/
A Dald_qspi.c394 ald_status_t ald_qspi_indac_transmit_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, ui… in ald_qspi_indac_transmit_by_it() argument
422 MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, saddr); in ald_qspi_indac_transmit_by_it()
444 ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, … in ald_qspi_indac_transmit_by_poll() argument
454 MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, saddr); in ald_qspi_indac_transmit_by_poll()
503 ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uin… in ald_qspi_indac_read_by_poll() argument
515 MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, saddr); in ald_qspi_indac_read_by_poll()
570 ald_status_t ald_qspi_indac_read_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint1… in ald_qspi_indac_read_by_it() argument
586 MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, saddr); in ald_qspi_indac_read_by_it()
/bsp/upd70f3454/
A Dlnk70f3454.xcl118 // SADDR_BASE is an empty segment that mark the beginning of the saddr
/bsp/at32/libraries/rt_drivers/
A Ddrv_hard_i2c.c165 i2c_x->ctrl2_bit.saddr = 0; in i2c_reset_ctrl2_register()

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