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Searched refs:shift (Results 1 – 25 of 137) sorted by relevance

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/bsp/rockchip/common/rk_hal/lib/hal/src/cru/
A Dhal_cru.c86 #define PLL_GET_PLLMODE(val, shift, mask) (((uint32_t)(val) & mask) >> shift) argument
648 ret = (HAL_Check)(!((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift)); in HAL_CRU_ClkIsEnabled()
666 CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); in HAL_CRU_ClkEnable()
675 CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); in HAL_CRU_ClkEnable()
693 CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); in HAL_CRU_ClkDisable()
702 CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); in HAL_CRU_ClkDisable()
726 ret = (HAL_Check)((CRU->CRU_CLKGATE_CON[index] & (1 << shift)) >> shift); in HAL_CRU_ClkIsReset()
745 CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); in HAL_CRU_ClkResetAssert()
750 CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); in HAL_CRU_ClkResetAssert()
769 CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); in HAL_CRU_ClkResetDeassert()
[all …]
/bsp/apm32/libraries/APM32S10x_Library/APM32S10x_StdPeriphDriver/src/
A Dapm32s10x_gpio.c108 uint32_t shift; in GPIO_Config() local
121 for (i = 0, shift = 0x01; i < 8; i++, shift <<= 1) in GPIO_Config()
123 if (gpioConfig->pin & shift) in GPIO_Config()
131 port->BC = shift; in GPIO_Config()
135 port->BSC = shift; in GPIO_Config()
147 for (i = 8, shift = 0x100; i < 16; i++, shift <<= 1) in GPIO_Config()
149 if (gpioConfig->pin & shift) in GPIO_Config()
157 port->BC = shift; in GPIO_Config()
161 port->BSC = shift; in GPIO_Config()
485 uint32_t shift; in GPIO_ConfigEINTLine() local
[all …]
/bsp/apm32/libraries/APM32E10x_Library/APM32E10x_StdPeriphDriver/src/
A Dapm32e10x_gpio.c116 uint32_t shift; in GPIO_Config() local
129 for (i = 0, shift = 0x01; i < 8; i++, shift <<= 1) in GPIO_Config()
131 if (gpioConfig->pin & shift) in GPIO_Config()
139 port->BC = shift; in GPIO_Config()
143 port->BSC = shift; in GPIO_Config()
155 for (i = 8, shift = 0x100; i < 16; i++, shift <<= 1) in GPIO_Config()
157 if (gpioConfig->pin & shift) in GPIO_Config()
165 port->BC = shift; in GPIO_Config()
169 port->BSC = shift; in GPIO_Config()
513 uint32_t shift; in GPIO_ConfigEINTLine() local
[all …]
/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/
A Dapm32f10x_gpio.c116 uint32_t shift; in GPIO_Config() local
129 for (i = 0, shift = 0x01; i < 8; i++, shift <<= 1) in GPIO_Config()
131 if (gpioConfig->pin & shift) in GPIO_Config()
139 port->BC = shift; in GPIO_Config()
143 port->BSC = shift; in GPIO_Config()
155 for (i = 8, shift = 0x100; i < 16; i++, shift <<= 1) in GPIO_Config()
157 if (gpioConfig->pin & shift) in GPIO_Config()
165 port->BC = shift; in GPIO_Config()
169 port->BSC = shift; in GPIO_Config()
531 uint32_t shift; in GPIO_ConfigEINTLine() local
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi-ng/
A Dccu_nkmp.c21 unsigned int shift; in ilog2() local
24 shift = (v > 0xff) << 3; in ilog2()
25 v >>= shift; in ilog2()
26 r |= shift; in ilog2()
27 shift = (v > 0xf) << 2; in ilog2()
28 v >>= shift; in ilog2()
29 r |= shift; in ilog2()
30 shift = (v > 0x3) << 1; in ilog2()
31 v >>= shift; in ilog2()
32 r |= shift; in ilog2()
[all …]
A Dccu_mp.c14 unsigned int shift; in ilog2() local
18 v >>= shift; in ilog2()
19 r |= shift; in ilog2()
20 shift = (v > 0xf) << 2; in ilog2()
21 v >>= shift; in ilog2()
22 r |= shift; in ilog2()
23 shift = (v > 0x3) << 1; in ilog2()
24 v >>= shift; in ilog2()
25 r |= shift; in ilog2()
253 reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift); in ccu_mp_set_rate()
[all …]
A Dccu_nkm.c84 n = reg >> nkm->n.shift; in ccu_nkm_recalc_rate()
92 k = reg >> nkm->k.shift; in ccu_nkm_recalc_rate()
100 m = reg >> nkm->m.shift; in ccu_nkm_recalc_rate()
185 reg &= ~GENMASK(nkm->n.width + nkm->n.shift - 1, nkm->n.shift); in ccu_nkm_set_rate()
186 reg &= ~GENMASK(nkm->k.width + nkm->k.shift - 1, nkm->k.shift); in ccu_nkm_set_rate()
187 reg &= ~GENMASK(nkm->m.width + nkm->m.shift - 1, nkm->m.shift); in ccu_nkm_set_rate()
189 reg |= (_nkm.n - nkm->n.offset) << nkm->n.shift; in ccu_nkm_set_rate()
190 reg |= (_nkm.k - nkm->k.offset) << nkm->k.shift; in ccu_nkm_set_rate()
191 reg |= (_nkm.m - nkm->m.offset) << nkm->m.shift; in ccu_nkm_set_rate()
A Dccu_nk.c78 n = reg >> nk->n.shift; in ccu_nk_recalc_rate()
86 k = reg >> nk->k.shift; in ccu_nk_recalc_rate()
153 reg &= ~GENMASK(nk->n.width + nk->n.shift - 1, nk->n.shift); in ccu_nk_set_rate()
154 reg &= ~GENMASK(nk->k.width + nk->k.shift - 1, nk->k.shift); in ccu_nk_set_rate()
156 reg |= (_nk.k - nk->k.offset) << nk->k.shift; in ccu_nk_set_rate()
157 reg |= (_nk.n - nk->n.offset) << nk->n.shift; in ccu_nk_set_rate()
A Dccu_nm.c103 n = reg >> nm->n.shift; in ccu_nm_recalc_rate()
111 m = reg >> nm->m.shift; in ccu_nm_recalc_rate()
221 reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift); in ccu_nm_set_rate()
258 reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift); in ccu_nm_set_rate()
259 reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift); in ccu_nm_set_rate()
261 reg |= (_nm.n - nm->n.offset) << nm->n.shift; in ccu_nm_set_rate()
262 reg |= (_nm.m - nm->m.offset) << nm->m.shift; in ccu_nm_set_rate()
/bsp/allwinner/libraries/sunxi-hal/hal/source/tpadc/
A Dcommon_tpadc.h41 #define SETMASK(width, shift) ((width?((-1U) >> (32-width)):0) << (shift)) argument
42 #define CLRMASK(width, shift) (~(SETMASK(width, shift))) argument
43 #define GET_BITS(shift, width, reg) \ argument
44 (((reg) & SETMASK(width, shift)) >> (shift))
45 #define SET_BITS(shift, width, reg, val) \ argument
46 (((reg) & CLRMASK(width, shift)) | (val << (shift)))
/bsp/allwinner/libraries/sunxi-hal/include/hal/
A Dsunxi_hal_pwm.h66 #define SETMASK(width, shift) ((width?((-1U) >> (32-width)):0) << (shift)) argument
67 #define CLRMASK(width, shift) (~(SETMASK(width, shift))) argument
68 #define GET_BITS(shift, width, reg) \ argument
69 (((reg) & SETMASK(width, shift)) >> (shift))
70 #define SET_BITS(shift, width, reg, val) \ argument
71 (((reg) & CLRMASK(width, shift)) | (val << (shift)))
A Dsunxi_hal_rtc.h52 #define SUNXI_GET(x, mask, shift) (((x) & ((mask) << (shift))) \ argument
53 >> (shift))
55 #define SUNXI_SET(x, mask, shift) (((x) & (mask)) << (shift)) argument
84 #define SUNXI_LEAP_SET_VALUE(x, shift) SUNXI_SET(x, SUNXI_MASK_LY, shift) argument
/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/
A Dhal_soc_eu_periph.h139 int shift = evt % 32; in hal_soc_eu_set_fc_mask() local
141 soc_eu_fc_write(soc_eu_fc_read(reg_offset) & ~(1 << shift), reg_offset); in hal_soc_eu_set_fc_mask()
148 int shift = evt % 32; in hal_soc_eu_set_pr_mask() local
150 soc_eu_pr_write(soc_eu_pr_read(reg_offset) & ~(1 << shift), reg_offset); in hal_soc_eu_set_pr_mask()
157 int shift = evt % 32; in hal_soc_eu_set_cl_mask() local
166 int shift = evt % 32; in hal_soc_eu_clear_fc_mask() local
168 soc_eu_fc_write(soc_eu_fc_read(reg_offset) | (1 << shift), reg_offset); in hal_soc_eu_clear_fc_mask()
175 int shift = evt % 32; in hal_soc_eu_clear_pr_mask() local
177 soc_eu_pr_write(soc_eu_pr_read(reg_offset) | (1 << shift), reg_offset); in hal_soc_eu_clear_pr_mask()
184 int shift = evt % 32; in hal_soc_eu_clear_cl_mask() local
[all …]
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_usbfs_library/host/class/hid/Source/
A Dusbh_hid_parser.c49 uint8_t shift = ri->shift; in hid_item_read() local
62 bofs += shift; in hid_item_read()
66 shift = (uint8_t)(bofs % 8U); in hid_item_read()
74 val=(val >> shift) & ((1U << ri->size) - 1U); in hid_item_read()
112 uint8_t shift = ri->shift; in hid_item_write() local
127 bofs += shift; in hid_item_write()
131 shift = (uint8_t)(bofs % 8U); in hid_item_write()
141 value = (value & mask) << shift; in hid_item_write()
/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/
A Dclk.h80 #define SETMASK(width, shift) ((width?((-1U) >> (32-width)):0) << (shift)) argument
81 #define CLRMASK(width, shift) (~(SETMASK(width, shift))) argument
83 #define SET_BITS(shift, width, reg, val) \ argument
84 (((reg) & CLRMASK(width, shift)) | (val << (shift)))
86 #define GET_BITS(shift, width, reg) \ argument
87 (((reg) & SETMASK(width, shift)) >> (shift))
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_trgm_drv.h100 uint8_t shift; in trgm_input_filter_set_filter_length() local
101 …for (shift = 0; shift <= (TRGM_FILTCFG_FILTLEN_SHIFT_MASK >> TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT); sh… in trgm_input_filter_set_filter_length()
102 if (shift > 0) { in trgm_input_filter_set_filter_length()
111 shift = (TRGM_FILTCFG_FILTLEN_SHIFT_MASK >> TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT); in trgm_input_filter_set_filter_length()
114 … | TRGM_FILTCFG_FILTLEN_BASE_SET(len) | TRGM_FILTCFG_FILTLEN_SHIFT_SET(shift); in trgm_input_filter_set_filter_length()
128 static inline void trgm_input_filter_set_filter_shift(TRGM_Type *ptr, uint8_t input, uint8_t shift) in trgm_input_filter_set_filter_shift() argument
132 | TRGM_FILTCFG_FILTLEN_SHIFT_SET(shift); in trgm_input_filter_set_filter_shift()
136 (void) shift; in trgm_input_filter_set_filter_shift()
/bsp/rockchip/common/rk_hal/lib/hal/src/
A Dhal_pwr.c42 #define WM_SET_BITS(msk, shift, bits) ((msk <<(shift + 16)) | (bits << shift)) argument
43 #define WM_SET_BIT(shift) ((1 << (16 + shift) ) | (1 << shift)) argument
44 #define WM_CLR_BIT(shift) (1 << (16 + shift) ) argument
73 val = WM_SET_BITS(desc->voltMask, desc->shift[ctrlType], val); in PWR_SetVoltage_Linear()
108 val = (READ_REG(*preg) >> desc->shift[ctrlType]) & desc->voltMask; in PWR_GetVoltageLinear()
125 val = WM_SET_BIT(desc->shift[PWR_CTRL_PWR_EN]); in PWR_EnableDisable()
127 val = WM_CLR_BIT(desc->shift[PWR_CTRL_PWR_EN]); in PWR_EnableDisable()
157 return (READ_REG(*preg) >> desc->shift[PWR_CTRL_PWR_EN]) & 0x1; in HAL_PWR_GetEnableState()
/bsp/allwinner/libraries/sunxi-hal/hal/source/sound/component/aw-alsa-lib/external_resample/speexrate/
A Darch.h157 #define SHR16(a,shift) (a) argument
158 #define SHL16(a,shift) (a) argument
159 #define SHR32(a,shift) (a) argument
160 #define SHL32(a,shift) (a) argument
161 #define PSHR16(a,shift) (a) argument
162 #define PSHR32(a,shift) (a) argument
163 #define VSHR32(a,shift) (a) argument
166 #define SATURATE32PSHR(x,shift,a) (x) argument
168 #define PSHR(a,shift) (a) argument
169 #define SHR(a,shift) (a) argument
[all …]
/bsp/mm32/libraries/MM32F3270_HAL/MM32F3270_HAL_Driver/Src/
A Dhal_gpio.c113 uint32_t shift = 0u; in GPIO_PinAFConf() local
120 shift = idx * 4u; in GPIO_PinAFConf()
121 val &= ~(0xFu << shift); in GPIO_PinAFConf()
122 val |= (uint32_t)af << shift; in GPIO_PinAFConf()
133 shift = (idx - 8u) * 4u; in GPIO_PinAFConf()
134 val &= ~(0xFu << shift); in GPIO_PinAFConf()
135 val |= (uint32_t)af << shift; in GPIO_PinAFConf()
/bsp/allwinner/libraries/sunxi-hal/hal/source/ledc/
A Dhal_ledc.c103 unsigned int shift = 21; in ledc_set_t1h_ns() local
114 reg_val &= ~(mask << shift); in ledc_set_t1h_ns()
115 reg_val |= n << shift; in ledc_set_t1h_ns()
123 unsigned int shift = 16; in ledc_set_t1l_ns() local
134 reg_val &= ~(mask << shift); in ledc_set_t1l_ns()
135 reg_val |= n << shift; in ledc_set_t1l_ns()
143 unsigned int shift = 6; in ledc_set_t0h_ns() local
155 reg_val |= n << shift; in ledc_set_t0h_ns()
215 unsigned int shift = 16; in ledc_set_wait_data_time_ns() local
230 reg_val |= (n << shift); in ledc_set_wait_data_time_ns()
[all …]
/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/
A Dhal_gpio.c300 u8 shift = (pin & 0x07) * 4; in GPIO_PinAFConfig() local
302 *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift); in GPIO_PinAFConfig()
320 u8 shift; in exGPIO_PinAFConfig() local
332 shift = (pin & 0x07) * 4; in exGPIO_PinAFConfig()
334 *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift); in exGPIO_PinAFConfig()
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_qeiv2_drv.c123 uint8_t shift; in qeiv2_config_filter() local
124 for (shift = 0; shift <= 7u; shift++) { in qeiv2_config_filter()
125 if (shift > 0) { in qeiv2_config_filter()
134 shift = 7u; in qeiv2_config_filter()
138 …DE_SET(mode) | QEIV2_FILT_CFG_SYNCEN_SET(sync) | QEIV2_FILT_CFG_FILTLEN_SET(((shift << 9u) | len)); in qeiv2_config_filter()
/bsp/rockchip/rk3500/driver/clk/
A Dclk-mmc-phase.c31 static rt_err_t rk_clk_mmc_set_phase(rt_ubase_t rate, void *reg, int shift, in rk_clk_mmc_set_phase() argument
92 HWREG32(reg) = HIWORD_UPDATE(raw_value, 0x07ff, shift); in rk_clk_mmc_set_phase()
97 static rt_base_t rk_clk_mmc_get_phase(rt_ubase_t rate, void *reg, int shift) in rk_clk_mmc_get_phase() argument
108 raw_value = HWREG32(reg) >> shift; in rk_clk_mmc_get_phase()
/bsp/rockchip/rk3500/driver/
A Drockchip.h20 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16)) argument
/bsp/nuvoton/libraries/nuc980/rtt_port/
A Ddrv_sys.c64 rt_uint32_t shift; in rt_hw_interrupt_set_priority() local
70 shift = (vector % 4) * 8; in rt_hw_interrupt_set_priority()
72 outpw(_mRegAddr, (inpw(_mRegAddr) & ~(0x07 << shift)) | (IntTypeLevel << shift)); in rt_hw_interrupt_set_priority()
172 rt_uint32_t shift; in rt_hw_interrupt_set_type() local
178 shift = (vector % 4) * 8; in rt_hw_interrupt_set_type()
180 outpw(_mRegAddr, (inpw(_mRegAddr) & ~(0xC0 << shift)) | (type << shift)); in rt_hw_interrupt_set_type()

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