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Searched refs:spi_base (Results 1 – 23 of 23) sorted by relevance

/bsp/loongson/ls1cdev/libraries/
A Dls1c_spi.c53 void ls1c_spi_print_all_regs_info(void *spi_base) in ls1c_spi_print_all_regs_info() argument
57 reg_read_8(spi_base + LS1C_SPI_SPCR_OFFSET), in ls1c_spi_print_all_regs_info()
58 reg_read_8(spi_base + LS1C_SPI_SPSR_OFFSET), in ls1c_spi_print_all_regs_info()
146 val = reg_read_8(spi_base + LS1C_SPI_SPCR_OFFSET); in ls1c_spi_set_clock()
149 reg_write_8(val, spi_base + LS1C_SPI_SPCR_OFFSET); in ls1c_spi_set_clock()
152 val = reg_read_8(spi_base + LS1C_SPI_SPER_OFFSET); in ls1c_spi_set_clock()
155 reg_write_8(val, spi_base + LS1C_SPI_SPER_OFFSET); in ls1c_spi_set_clock()
171 val = reg_read_8(spi_base + LS1C_SPI_SPCR_OFFSET); in ls1c_spi_set_mode()
181 reg_write_8(val, spi_base + LS1C_SPI_SPCR_OFFSET); in ls1c_spi_set_mode()
217 void ls1c_spi_wait_txrx_done(void *spi_base) in ls1c_spi_wait_txrx_done() argument
[all …]
A Dls1c_spi.h89 void ls1c_spi_set_clock(void *spi_base, unsigned long max_hz);
98 void ls1c_spi_set_mode(void *spi_base, unsigned char cpol, unsigned char cpha);
107 void ls1c_spi_set_cs(void *spi_base, unsigned char cs, int new_status);
119 unsigned char ls1c_spi_txrx_byte(void *spi_base, unsigned char tx_ch);
126 void ls1c_spi_print_all_regs_info(void *spi_base);
/bsp/nuvoton/libraries/m2354/rtt_port/
A Ddrv_spi.c85 .spi_base = SPI0,
101 .spi_base = SPI1,
118 .spi_base = SPI2,
135 .spi_base = SPI3,
278 SPI_T *spi_base = spi_bus->spi_base; in nu_pdma_spi_rx_config() local
326 SPI_T *spi_base = spi_bus->spi_base; in nu_pdma_spi_tx_config() local
371 SPI_T *spi_base = spi_bus->spi_base; in nu_spi_pdma_transmit() local
428 while (SPI_IS_BUSY(spi_base)); in nu_spi_drain_rxfifo()
433 SPI_ClearRxFIFO(spi_base); in nu_spi_drain_rxfifo()
510 SPI_T *spi_base = spi_bus->spi_base; in nu_spi_transmission_with_poll() local
[all …]
A Ddrv_qspi.c59 .spi_base = (SPI_T *)QSPI0,
119 u32BusClock = QSPI_SetBusClock((QSPI_T *)spi_bus->spi_base, configuration->max_hz); in nu_qspi_bus_configure()
131 …QSPI_Open((QSPI_T *)spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, u32BusCl… in nu_qspi_bus_configure()
136 SPI_SET_SS_LOW(spi_bus->spi_base); in nu_qspi_bus_configure()
141 SPI_SET_SS_HIGH(spi_bus->spi_base); in nu_qspi_bus_configure()
147 SPI_SET_MSB_FIRST(spi_bus->spi_base); in nu_qspi_bus_configure()
152 SPI_SET_LSB_FIRST(spi_bus->spi_base); in nu_qspi_bus_configure()
157 nu_spi_drain_rxfifo(spi_bus->spi_base); in nu_qspi_bus_configure()
166 QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base; in nu_qspi_mode_config()
226 qspi_base = (QSPI_T *)qspi_bus->spi_base; in nu_qspi_bus_xfer()
A Ddrv_spi.h30 SPI_T *spi_base; member
44 void nu_spi_drain_rxfifo(SPI_T *spi_base);
/bsp/nuvoton/libraries/m480/rtt_port/
A Ddrv_spi.c85 .spi_base = SPI0,
101 .spi_base = SPI1,
118 .spi_base = SPI2,
135 .spi_base = SPI3,
278 SPI_T *spi_base = spi_bus->spi_base; in nu_pdma_spi_rx_config() local
326 SPI_T *spi_base = spi_bus->spi_base; in nu_pdma_spi_tx_config() local
371 SPI_T *spi_base = spi_bus->spi_base; in nu_spi_pdma_transmit() local
428 while (SPI_IS_BUSY(spi_base)); in nu_spi_drain_rxfifo()
433 SPI_ClearRxFIFO(spi_base); in nu_spi_drain_rxfifo()
510 SPI_T *spi_base = spi_bus->spi_base; in nu_spi_transmission_with_poll() local
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A Ddrv_qspi.c62 .spi_base = (SPI_T *)QSPI0,
78 .spi_base = (SPI_T *)QSPI1,
137 u32BusClock = QSPI_SetBusClock((QSPI_T *)spi_bus->spi_base, configuration->max_hz); in nu_qspi_bus_configure()
149 …QSPI_Open((QSPI_T *)spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, u32BusCl… in nu_qspi_bus_configure()
154 SPI_SET_SS_LOW(spi_bus->spi_base); in nu_qspi_bus_configure()
159 SPI_SET_SS_HIGH(spi_bus->spi_base); in nu_qspi_bus_configure()
165 SPI_SET_MSB_FIRST(spi_bus->spi_base); in nu_qspi_bus_configure()
170 SPI_SET_LSB_FIRST(spi_bus->spi_base); in nu_qspi_bus_configure()
175 nu_spi_drain_rxfifo(spi_bus->spi_base); in nu_qspi_bus_configure()
184 QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base; in nu_qspi_mode_config()
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A Ddrv_spi.h30 SPI_T *spi_base; member
45 void nu_spi_drain_rxfifo(SPI_T *spi_base);
/bsp/nuvoton/libraries/m460/rtt_port/
A Ddrv_spi.c106 .spi_base = SPI0,
122 .spi_base = SPI1,
138 .spi_base = SPI2,
154 .spi_base = SPI3,
171 .spi_base = SPI4,
189 .spi_base = SPI5,
207 .spi_base = SPI6,
225 .spi_base = SPI7,
443 SPI_T *spi_base = spi_bus->spi_base; in nu_pdma_spi_rx_config() local
506 SPI_T *spi_base = spi_bus->spi_base; in nu_pdma_spi_tx_config() local
[all …]
A Ddrv_qspi.c62 .spi_base = (SPI_T *)QSPI0,
78 .spi_base = (SPI_T *)QSPI1,
137 u32BusClock = QSPI_SetBusClock((QSPI_T *)spi_bus->spi_base, configuration->max_hz); in nu_qspi_bus_configure()
149 …QSPI_Open((QSPI_T *)spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, u32BusCl… in nu_qspi_bus_configure()
154 SPI_SET_SS_LOW(spi_bus->spi_base); in nu_qspi_bus_configure()
159 SPI_SET_SS_HIGH(spi_bus->spi_base); in nu_qspi_bus_configure()
165 SPI_SET_MSB_FIRST(spi_bus->spi_base); in nu_qspi_bus_configure()
170 SPI_SET_LSB_FIRST(spi_bus->spi_base); in nu_qspi_bus_configure()
175 nu_spi_drain_rxfifo(spi_bus->spi_base); in nu_qspi_bus_configure()
184 QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base; in nu_qspi_mode_config()
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A Ddrv_spi.h30 SPI_T *spi_base; member
45 void nu_spi_drain_rxfifo(SPI_T *spi_base);
/bsp/nuvoton/libraries/ma35/rtt_port/
A Ddrv_spi.c85 .spi_base = SPI0,
101 .spi_base = SPI1,
117 .spi_base = SPI2,
133 .spi_base = SPI3,
265 SPI_TRIGGER_TX_RX_PDMA(spi_base); in nu_pdma_spi_tx_cb_trigger()
274 SPI_DISABLE_TX_RX_PDMA(spi_base); in nu_pdma_spi_rx_cb_disable()
286 SPI_T *spi_base = spi_bus->spi_base; in nu_pdma_spi_rx_config() local
349 SPI_T *spi_base = spi_bus->spi_base; in nu_pdma_spi_tx_config() local
440 while (SPI_IS_BUSY(spi_base)); in nu_spi_drain_rxfifo()
445 SPI_ClearRxFIFO(spi_base); in nu_spi_drain_rxfifo()
[all …]
A Ddrv_qspi.c62 .spi_base = (SPI_T *)QSPI0,
78 .spi_base = (SPI_T *)QSPI1,
141 …u32ActualClk = QSPI_Open((QSPI_T *)spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_… in nu_qspi_bus_configure()
147 SPI_SET_SS_LOW(spi_bus->spi_base); in nu_qspi_bus_configure()
152 SPI_SET_SS_HIGH(spi_bus->spi_base); in nu_qspi_bus_configure()
158 SPI_SET_MSB_FIRST(spi_bus->spi_base); in nu_qspi_bus_configure()
163 SPI_SET_LSB_FIRST(spi_bus->spi_base); in nu_qspi_bus_configure()
168 nu_spi_drain_rxfifo(spi_bus->spi_base); in nu_qspi_bus_configure()
177 QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base; in nu_qspi_mode_config()
233 qspi_base = (QSPI_T *)qspi_bus->spi_base; in nu_qspi_bus_xfer()
A Ddrv_spi.h31 SPI_T *spi_base; member
46 void nu_spi_drain_rxfifo(SPI_T *spi_base);
/bsp/nuvoton/libraries/m031/rtt_port/
A Ddrv_spi.c62 void nu_spi_drain_rxfifo(SPI_T *spi_base);
76 .spi_base = SPI0,
218 SPI_T *spi_base = spi_bus->spi_base; in nu_pdma_spi_rx_config() local
266 SPI_T *spi_base = spi_bus->spi_base; in nu_pdma_spi_tx_config() local
311 SPI_T *spi_base = spi_bus->spi_base; in nu_spi_pdma_transmit() local
368 while (SPI_IS_BUSY(spi_base)); in nu_spi_drain_rxfifo()
373 SPI_ClearRxFIFO(spi_base); in nu_spi_drain_rxfifo()
389 val = SPI_READ_RX(spi_base); in nu_spi_read()
450 SPI_T *spi_base = spi_bus->spi_base; in nu_spi_transmission_with_poll() local
492 while (SPI_IS_BUSY(spi_base)) in nu_spi_transmission_with_poll()
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A Ddrv_qspi.c59 .spi_base = (SPI_T *)QSPI0,
119 u32BusClock = QSPI_SetBusClock((QSPI_T *)spi_bus->spi_base, configuration->max_hz); in nu_qspi_bus_configure()
131 …QSPI_Open((QSPI_T *)spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, u32BusCl… in nu_qspi_bus_configure()
136 SPI_SET_SS_LOW(spi_bus->spi_base); in nu_qspi_bus_configure()
141 SPI_SET_SS_HIGH(spi_bus->spi_base); in nu_qspi_bus_configure()
147 SPI_SET_MSB_FIRST(spi_bus->spi_base); in nu_qspi_bus_configure()
152 SPI_SET_LSB_FIRST(spi_bus->spi_base); in nu_qspi_bus_configure()
157 nu_spi_drain_rxfifo(spi_bus->spi_base); in nu_qspi_bus_configure()
166 QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base; in nu_qspi_mode_config()
226 qspi_base = (QSPI_T *)qspi_bus->spi_base; in nu_qspi_bus_xfer()
A Ddrv_spi.h30 SPI_T *spi_base; member
44 void nu_spi_drain_rxfifo(SPI_T *spi_base);
/bsp/nuvoton/libraries/nuc980/rtt_port/
A Ddrv_spi.c84 .spi_base = SPI0,
101 .spi_base = SPI1,
235 SPI_TRIGGER_TX_RX_PDMA(spi_base); in nu_pdma_spi_tx_cb_trigger()
244 SPI_DISABLE_TX_RX_PDMA(spi_base); in nu_pdma_spi_rx_cb_disable()
256 SPI_T *spi_base = spi_bus->spi_base; in nu_pdma_spi_rx_config() local
319 SPI_T *spi_base = spi_bus->spi_base; in nu_pdma_spi_tx_config() local
410 while (SPI_IS_BUSY(spi_base)); in nu_spi_drain_rxfifo()
415 SPI_ClearRxFIFO(spi_base); in nu_spi_drain_rxfifo()
492 SPI_T *spi_base = spi_bus->spi_base; in nu_spi_transmission_with_poll() local
534 while (SPI_IS_BUSY(spi_base)) in nu_spi_transmission_with_poll()
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A Ddrv_qspi.c59 .spi_base = (SPI_T *)QSPI0,
123 …QSPI_Open((QSPI_T *)spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, configur… in nu_qspi_bus_configure()
128 SPI_SET_SS_LOW(spi_bus->spi_base); in nu_qspi_bus_configure()
133 SPI_SET_SS_HIGH(spi_bus->spi_base); in nu_qspi_bus_configure()
139 SPI_SET_MSB_FIRST(spi_bus->spi_base); in nu_qspi_bus_configure()
144 SPI_SET_LSB_FIRST(spi_bus->spi_base); in nu_qspi_bus_configure()
149 nu_spi_drain_rxfifo(spi_bus->spi_base); in nu_qspi_bus_configure()
158 QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base; in nu_qspi_mode_config()
214 qspi_base = (QSPI_T *)qspi_bus->spi_base; in nu_qspi_bus_xfer()
A Ddrv_spi.h30 SPI_T *spi_base; member
46 void nu_spi_drain_rxfifo(SPI_T *spi_base);
/bsp/loongson/ls1cdev/drivers/
A Ddrv_spi.c46 void *spi_base = NULL; in configure() local
57 spi_base = ls1c_spi_get_base(SPIx); in configure()
61 reg_write_8(0x53, spi_base + LS1C_SPI_SPCR_OFFSET); in configure()
64 reg_write_8(0xc0, spi_base + LS1C_SPI_SPSR_OFFSET); in configure()
79 ls1c_spi_set_clock(spi_base, configuration->max_hz); in configure()
98 ls1c_spi_set_mode(spi_base, cpol, cpha); in configure()
111 void *spi_base = NULL; in xfer() local
126 spi_base = ls1c_spi_get_base(SPIx); in xfer()
136 ls1c_spi_set_cs(spi_base, cs, 0); in xfer()
156 ls1c_spi_txrx_byte(spi_base, data); in xfer()
[all …]
/bsp/hpmicro/libraries/drivers/
A Ddrv_spi.c33 SPI_Type *spi_base; member
46 void (*spi_pins_init)(SPI_Type *spi_base);
57 .spi_base = HPM_SPI0,
74 .spi_base = HPM_SPI1,
91 .spi_base = HPM_SPI2,
108 .spi_base = HPM_SPI3,
125 .spi_base = HPM_SPI4,
142 .spi_base = HPM_SPI5,
159 .spi_base = HPM_SPI6,
176 .spi_base = HPM_SPI7,
[all …]
/bsp/nuvoton/libraries/nu_packages/SPINAND/
A Ddrv_spinand.c899 SPI_SET_MRXPHASE(psNuSpiBus->spi_base, j); in find_valid_window()

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