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Searched refs:t3 (Results 1 – 25 of 28) sorted by relevance

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/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r908/
A Dvectors.S106 csrr t3, mstatus
179 csrr t3, mhartid
195 mul t2, t2, t3
218 addi t1, t3, 1
263 csrr t3, mstatus
274 csrr t3, mhartid
282 mul t2, t2, t3
358 mul t2, t2, t3
527 csrr t3, sstatus
609 csrr t3, mstatus
[all …]
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c907/
A Dvectors.S59 store_x t3, (48+48)(sp)
83 store_x t3, (48)(sp)
90 csrr t3, sstatus
151 load_x t3, (48)(sp)
222 store_x t3, (48)(sp)
229 csrr t3, mstatus
290 load_x t3, (48)(sp)
355 store_x t3, (48)(sp)
362 csrr t3, sstatus
499 csrr t3, mstatus
[all …]
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/
A Dvectors.S58 sd t3, (48+48)(sp)
64 csrr t3, sstatus
97 ld t3, (48+48)(sp)
133 sd t3, (48+48)(sp)
139 csrr t3, mstatus
172 ld t3, (48+48)(sp)
207 sd t3, (48+48)(sp)
213 csrr t3, sstatus
246 ld t3, (48+48)(sp)
285 sd t3, (48+48)(sp)
[all …]
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c920v3/
A Dvectors.S57 sd t3, (48+48)(sp)
63 csrr t3, sstatus
96 ld t3, (48+48)(sp)
140 sd t3, (48+48)(sp)
146 csrr t3, mstatus
179 ld t3, (48+48)(sp)
227 sd t3, (48+48)(sp)
232 csrr t3, mstatus
265 ld t3, (48+48)(sp)
309 csrr t3, sstatus
[all …]
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r910/
A Dvectors.S58 sd t3, (48+48)(sp)
64 csrr t3, sstatus
97 ld t3, (48+48)(sp)
142 sd t3, (48+48)(sp)
148 csrr t3, mstatus
181 ld t3, (48+48)(sp)
230 sd t3, (48+48)(sp)
236 csrr t3, mstatus
269 ld t3, (48+48)(sp)
314 csrr t3, sstatus
[all …]
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908v/
A Dvectors.S58 sd t3, (48+48)(sp)
64 csrr t3, sstatus
97 ld t3, (48+48)(sp)
142 sd t3, (48+48)(sp)
148 csrr t3, mstatus
181 ld t3, (48+48)(sp)
230 sd t3, (48+48)(sp)
236 csrr t3, mstatus
269 ld t3, (48+48)(sp)
314 csrr t3, sstatus
[all …]
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c910v3/
A Dvectors.S57 sd t3, (48+48)(sp)
63 csrr t3, sstatus
96 ld t3, (48+48)(sp)
140 sd t3, (48+48)(sp)
146 csrr t3, mstatus
179 ld t3, (48+48)(sp)
227 sd t3, (48+48)(sp)
232 csrr t3, mstatus
265 ld t3, (48+48)(sp)
309 csrr t3, sstatus
[all …]
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/r920/
A Dvectors.S58 sd t3, (48+48)(sp)
64 csrr t3, sstatus
97 ld t3, (48+48)(sp)
142 sd t3, (48+48)(sp)
148 csrr t3, mstatus
181 ld t3, (48+48)(sp)
230 sd t3, (48+48)(sp)
236 csrr t3, mstatus
269 ld t3, (48+48)(sp)
314 csrr t3, sstatus
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/
A Dstart.S24 lw t3, 0(t2)
25 sw t3, 0(t2)
28 lw t3, 0(t2)
29 sw t3, 0(t2)
A Dvector.S111 sd t3, (48+48)(sp)
188 ld t3, (48+48)(sp)
225 sd t3, (48+48)(sp)
309 ld t3, (48+48)(sp)
350 sd t3, (48+48)(sp)
436 ld t3, (48+48)(sp)
475 sd t3, (48+48)(sp)
571 ld t3, (48+48)(sp)
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/
A Driscv_asm_macro.h92 load_x t3, (0)(sp)
93 csrw mstatus, t3
142 load_x t3, (0)(sp)
143 csrw sstatus, t3
156 and t4, t3, t1
234 and t4, t3, t1
311 and t4, t3, t1
351 and t4, t3, t1
404 and t4, t3, t1
444 and t4, t3, t1
[all …]
/bsp/loongson/ls1cdev/drivers/
A Dselfboot_gcc.S193 li t3, (0x00008003 | (CPU_DIV << 8)) /* set CPU DEV */
198 sw t3, 0x4(t0) /* write CLK_DIV_PARAM */
371 and t3, t0, 0x0000ffff /* t3 = t0 & 0x0000ffff, get low 16 bit */
372 bnez t3, 2f /* if t3 != 0, jump to next tag 2 */
375 lw t3, 0(t1) /* copy 4 bit from memory address t1 to register t3 */
377 sw t3, 0(t0) /* copy 4 bit from register t3 to memory address in t0 */
487 srl t3, v0, 16 /* t3 = v0 >> 16 Icache组相联数 IA */
493 sll t5, t3 //t5 InstCacheSize
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e907/
A Dvectors.S76 sw t3, 48(sp)
88 csrr t3, mstatus
147 lw t3, 48(sp)
229 sw t3, 48(sp)
241 csrr t3, mstatus
309 lw t3, 48(sp)
363 lw t3, 48(sp)
484 sw t3, 48(sp)
496 csrr t3, mstatus
555 lw t3, 48(sp)
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e906/
A Dvectors.S76 sw t3, 48(sp)
88 csrr t3, mstatus
147 lw t3, 48(sp)
228 sw t3, 48(sp)
240 csrr t3, mstatus
308 lw t3, 48(sp)
362 lw t3, 48(sp)
483 sw t3, 48(sp)
495 csrr t3, mstatus
558 lw t3, 48(sp)
/bsp/thead-smart/drivers/
A Dvectors.S56 la t3, irq_mstatus_fs_flag
57 sw t1, (t3)
236 sw t3, 48(sp)
306 lw t3, 48(sp)
/bsp/yichip/yc3122-pos/Libraries/startup/
A Dstartup_rv32.s103 li t3,0x01
106 and t4, t1, t3
109 slli t3, t3, 1
/bsp/nxp/imx/imxrt/libraries/drivers/vglite/VGLite/
A Dvg_lite_flat.c327 const vg_lite_float_t t3 = t * t2; in cubic_bezier_eval() local
329 *x = omt3 * c->X0 + 3.0 * t * omt2 * c->X1 + 3.0 * t2 * omt * c->X2 + t3 * c->X3; in cubic_bezier_eval()
330 *y = omt3 * c->Y0 + 3.0 * t * omt2 * c->Y1 + 3.0 * t2 * omt * c->Y2 + t3 * c->Y3; in cubic_bezier_eval()
/bsp/hpmicro/hpm6300evk/startup/HPM6360/
A Dtrap.c78 RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); in rt_show_stack_frame()
/bsp/hpmicro/hpm6750evk/startup/HPM6750/
A Dtrap.c78 RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); in rt_show_stack_frame()
/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/
A Dtrap.c78 RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); in rt_show_stack_frame()
/bsp/hpmicro/hpm5300evk/startup/HPM5361/
A Dtrap.c78 RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); in rt_show_stack_frame()
/bsp/hpmicro/hpm5301evklite/startup/HPM5301/
A Dtrap.c78 RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); in rt_show_stack_frame()
/bsp/hpmicro/hpm6200evk/startup/HPM6280/
A Dtrap.c78 RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); in rt_show_stack_frame()
/bsp/hpmicro/hpm6750evk2/startup/HPM6750/
A Dtrap.c78 RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); in rt_show_stack_frame()
/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/
A Dtrap.c78 RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); in rt_show_stack_frame()

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