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Searched refs:tcd (Results 1 – 7 of 7) sorted by relevance

/bsp/frdm-k64f/device/MK64F12/
A Dfsl_edma.c102 assert(tcd != NULL); in EDMA_InstallTCD()
265 tcd->SADDR = 0U; in EDMA_TcdReset()
266 tcd->SOFF = 0U; in EDMA_TcdReset()
267 tcd->ATTR = 0U; in EDMA_TcdReset()
268 tcd->NBYTES = 0U; in EDMA_TcdReset()
269 tcd->SLAST = 0U; in EDMA_TcdReset()
270 tcd->DADDR = 0U; in EDMA_TcdReset()
271 tcd->DOFF = 0U; in EDMA_TcdReset()
272 tcd->CITER = 0U; in EDMA_TcdReset()
276 tcd->BITER = 0U; in EDMA_TcdReset()
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A Dfsl_edma.h522 void EDMA_TcdReset(edma_tcd_t *tcd);
593 static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) in EDMA_TcdSetBandWidth() argument
595 assert(tcd != NULL); in EDMA_TcdSetBandWidth()
596 assert(((uint32_t)tcd & 0x1FU) == 0); in EDMA_TcdSetBandWidth()
598 tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); in EDMA_TcdSetBandWidth()
622 static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) in EDMA_TcdEnableAutoStopRequest() argument
624 assert(tcd != NULL); in EDMA_TcdEnableAutoStopRequest()
625 assert(((uint32_t)tcd & 0x1FU) == 0); in EDMA_TcdEnableAutoStopRequest()
627 tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); in EDMA_TcdEnableAutoStopRequest()
637 void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask);
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A Dfsl_sai_edma.h61 edma_tcd_t tcd[SAI_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ member
A Dfsl_sai_edma.c150 EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); in SAI_TransferTxCreateHandleEDMA()
178 EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); in SAI_TransferRxCreateHandleEDMA()
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_edma.c71 assert(tcd != NULL); in EDMA_InstallTCD()
234 tcd->SADDR = 0U; in EDMA_TcdReset()
235 tcd->SOFF = 0U; in EDMA_TcdReset()
236 tcd->ATTR = 0U; in EDMA_TcdReset()
237 tcd->NBYTES = 0U; in EDMA_TcdReset()
238 tcd->SLAST = 0U; in EDMA_TcdReset()
239 tcd->DADDR = 0U; in EDMA_TcdReset()
240 tcd->DOFF = 0U; in EDMA_TcdReset()
241 tcd->CITER = 0U; in EDMA_TcdReset()
245 tcd->BITER = 0U; in EDMA_TcdReset()
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A Dfsl_edma.h282 void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd);
496 void EDMA_TcdReset(edma_tcd_t *tcd);
569 assert(tcd != NULL); in EDMA_TcdSetBandWidth()
570 assert(((uint32_t)tcd & 0x1FU) == 0); in EDMA_TcdSetBandWidth()
572 tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); in EDMA_TcdSetBandWidth()
596 static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) in EDMA_TcdEnableAutoStopRequest() argument
598 assert(tcd != NULL); in EDMA_TcdEnableAutoStopRequest()
599 assert(((uint32_t)tcd & 0x1FU) == 0); in EDMA_TcdEnableAutoStopRequest()
601 tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); in EDMA_TcdEnableAutoStopRequest()
611 void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask);
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A Dfsl_lpi2c_edma.c239 edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_32_MASK)); in LPI2C_MasterTransferEDMA() local
265 EDMA_TcdReset(tcd); in LPI2C_MasterTransferEDMA()
266 EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); in LPI2C_MasterTransferEDMA()
267 EDMA_TcdEnableInterrupts(tcd, kEDMA_MajorInterruptEnable); in LPI2C_MasterTransferEDMA()
268 linkTcd = tcd; in LPI2C_MasterTransferEDMA()
302 EDMA_TcdReset(tcd); in LPI2C_MasterTransferEDMA()
303 EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); in LPI2C_MasterTransferEDMA()
304 EDMA_TcdEnableInterrupts(tcd, kEDMA_MajorInterruptEnable); in LPI2C_MasterTransferEDMA()
305 linkTcd = tcd; in LPI2C_MasterTransferEDMA()

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