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Searched refs:tmpVal (Results 1 – 25 of 40) sorted by relevance

12

/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/
A Dbl702_glb.c3376 tmpVal = tmpVal | (1 << gpioPin); in GLB_GPIO_OUTPUT_Enable()
3395 tmpVal = tmpVal & ~(1 << gpioPin); in GLB_GPIO_OUTPUT_Disable()
3438 tmpVal = (tmpVal & 0xffffff00); in GLB_GPIO_Set_HZ()
3440 tmpVal = (tmpVal & 0xff00ffff); in GLB_GPIO_Set_HZ()
3457 tmpVal = (tmpVal & 0xffff00ff); in GLB_GPIO_Set_HZ()
3460 tmpVal = (tmpVal & 0x00ffffff); in GLB_GPIO_Set_HZ()
3485 tmpVal = (tmpVal & 0xffffff00); in GLB_Set_Flash_Pad_HZ()
3487 tmpVal = (tmpVal & 0xff00ffff); in GLB_Set_Flash_Pad_HZ()
3494 tmpVal = (tmpVal & 0xffff00ff); in GLB_Set_Flash_Pad_HZ()
3497 tmpVal = (tmpVal & 0x00ffffff); in GLB_Set_Flash_Pad_HZ()
[all …]
A Dbl702_aon.c113 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_Power_On_MBG()
137 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_Power_Off_MBG()
159 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON); in AON_Power_On_XTAL()
160 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON); in AON_Power_On_XTAL()
257 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON); in AON_Power_Off_XTAL()
279 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON); in AON_Power_On_BG()
301 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON); in AON_Power_Off_BG()
407 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON); in AON_Power_On_SFReg()
429 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON); in AON_Power_Off_SFReg()
455 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_LowPower_Enter_PDS0()
[all …]
A Dbl702_pds.c342 tmpVal = tmpVal | (1 << offset); in PDS_IntEn()
344 tmpVal = tmpVal & ~(1 << offset); in PDS_IntEn()
399 tmpVal = tmpVal | (1 << offset); in PDS_IntMask()
401 tmpVal = tmpVal & ~(1 << offset); in PDS_IntMask()
662 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_CLR); in PDS_Set_Vddcore_GPIO_IntClear()
666 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_INT_CLR); in PDS_Set_Vddcore_GPIO_IntClear()
670 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_CLR); in PDS_Set_Vddcore_GPIO_IntClear()
860 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL); in PDS_Power_On_PLL()
1024 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL); in PDS_Power_Off_PLL()
1117 tmpVal = tmpVal | (1 << 14); in PDS_Reset()
[all …]
A Dbl702_hbn.c303 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); in HBN_Enable_Ext()
327 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); in HBN_Reset()
330 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST); in HBN_Reset()
333 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); in HBN_Reset()
403 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_MODE); in HBN_Disable()
422 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN); in HBN_PIR_Enable()
441 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN); in HBN_PIR_Disable()
979 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K); in HBN_Power_On_RC32K()
1649 tmpVal = tmpVal | (1 << (gpioIrq + 8)); in HBN_GPIO_Dbg_Pull_Cfg()
1651 tmpVal = tmpVal & ~(1 << (gpioIrq + 8)); in HBN_GPIO_Dbg_Pull_Cfg()
[all …]
A Dbl702_l1c.c107 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Cache_Enable_Set()
108 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS); in L1C_Cache_Enable_Set()
109 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS); in L1C_Cache_Enable_Set()
110 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CNT_EN); in L1C_Cache_Enable_Set()
138 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN); in L1C_Cache_Enable_Set()
145 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_FLUSH_EN); in L1C_Cache_Enable_Set()
160 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN); in L1C_Cache_Enable_Set()
163 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS); in L1C_Cache_Enable_Set()
166 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BYPASS); in L1C_Cache_Enable_Set()
167 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CNT_EN); in L1C_Cache_Enable_Set()
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/
A Dbl616_glb.c475 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN); in GLB_Power_On_XTAL_And_PLL_CLK()
874 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB); in GLB_Set_USB_CLK_From_WIFIPLL()
878 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_USBPLL_RSTB); in GLB_Set_USB_CLK_From_WIFIPLL()
882 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB); in GLB_Set_USB_CLK_From_WIFIPLL()
914 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SSCDIV_RSTB); in GLB_Set_SSC_CLK_From_WIFIPLL()
918 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SSCDIV_RSTB); in GLB_Set_SSC_CLK_From_WIFIPLL()
1306 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN); in GLB_Set_IR_CLK()
1454 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); in GLB_Set_SF_CLK()
1522 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN); in GLB_Set_I2C_CLK()
1593 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN); in GLB_Set_SPI_CLK()
[all …]
A Dbl616_aon.c114 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_Power_On_MBG()
138 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_Power_Off_MBG()
160 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON); in AON_Power_On_XTAL()
237 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON); in AON_Power_Off_XTAL()
260 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON); in AON_Power_On_BG()
518 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_LowPower_Enter_PDS0()
523 tmpVal = tmpVal & (~(1 << 6)); in AON_LowPower_Enter_PDS0()
524 tmpVal = tmpVal & (~(1 << 7)); in AON_LowPower_Enter_PDS0()
544 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_LowPower_Exit_PDS0()
566 tmpVal = tmpVal | ((1 << 6)); in AON_LowPower_Exit_PDS0()
[all …]
A Dbl616_tzc_sec.c99 uint32_t tmpVal; in Tzc_Sec_Set_Sboot_Done() local
102 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, 0xf); in Tzc_Sec_Set_Sboot_Done()
108 uint32_t tmpVal; in Tzc_Sec_Set_Bus_Remap() local
113 tmpVal = BL_SET_REG_BIT(tmpVal, TZC_SEC_TZC_BUS_RMP_EN); in Tzc_Sec_Set_Bus_Remap()
115 tmpVal = BL_CLR_REG_BIT(tmpVal, TZC_SEC_TZC_BUS_RMP_EN); in Tzc_Sec_Set_Bus_Remap()
121 tmpVal = BL_SET_REG_BIT(tmpVal, TZC_SEC_TZC_BUS_RMP_EN_LOCK); in Tzc_Sec_Set_Bus_Remap()
127 uint32_t tmpVal; in Tzc_Sec_Set_Master_Group() local
147 uint32_t tmpVal; in Tzc_Sec_Set_Slave_Group() local
498 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_TZC_HBNRAM_R0_EN, 1); in Tzc_Sec_HBNRAM_Access_Set()
538 tmpVal = tmpVal & (0xff << (8 * region)); in Tzc_Sec_Flash_Access_Set()
[all …]
A Dbl616_psram.c114 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_PCK_S_DIV, 0x1); in PSram_Ctrl_Init()
127 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_WB_HYPER3); in PSram_Ctrl_Init()
148 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_CONFIG_REQ, 1); in PSram_Ctrl_Request()
430 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_GLB_RESET_PULSE); in PSram_Ctrl_ApMem_Reset()
450 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_WB_SW_RST); in PSram_Ctrl_Winbond_Reset()
473 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_CLKN_FREE); in PSram_Ctrl_CK_Sel()
475 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_REG_CLKN_FREE); in PSram_Ctrl_CK_Sel()
517 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_TIMEOUT_CLR); in PSram_Ctrl_Clear_Timout_Flag()
521 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_REG_TIMEOUT_CLR); in PSram_Ctrl_Clear_Timout_Flag()
545 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_TIMEOUT_EN); in PSram_Ctrl_Debug_Timout()
[all …]
A Dbl616_glb_gpio.c122 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE); in GLB_GPIO_Init()
153 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); in GLB_GPIO_Init()
154 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE); in GLB_GPIO_Init()
219 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); in GLB_GPIO_Input_Enable()
277 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); in GLB_GPIO_Input_Disable()
299 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE); in GLB_GPIO_Output_Enable()
321 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE); in GLB_GPIO_Output_Disable()
344 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE); in GLB_GPIO_Set_HZ()
349 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); in GLB_GPIO_Set_HZ()
350 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE); in GLB_GPIO_Set_HZ()
[all …]
A Dbl616_hbn.c201 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET); in HBN_Enable()
202 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP); in HBN_Enable()
257 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); in HBN_Enable()
280 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); in HBN_Reset()
283 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST); in HBN_Reset()
286 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); in HBN_Reset()
327 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN); in HBN_PIR_Enable()
347 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN); in HBN_PIR_Disable()
911 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K); in HBN_Keep_On_RC32K()
930 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_RC32K); in HBN_Power_Off_RC32K()
[all …]
A Dbl616_pds.c373 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_START_PS); in PDS_Disable_GPIO_Keep()
396 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_MCU1_CLK_EN); in PDS_Set_MCU0_Clock_Enable()
415 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_MCU1_CLK_EN); in PDS_Set_MCU0_Clock_Disable()
447 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_PU_CLKPLL); in PDS_Pu_PLL_Enable()
465 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_PU_CLKPLL); in PDS_Pu_PLL_Disable()
632 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); in PDS_IntClear()
636 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); in PDS_IntClear()
640 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); in PDS_IntClear()
729 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_PU_USB20_PSW); in PDS_Turn_On_USB()
740 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_USB_SW_RST_N); in PDS_Turn_On_USB()
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/
A Dbl602_glb.c174 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN); in GLB_Set_System_CLK_Div()
175 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN); in GLB_Set_System_CLK_Div()
2138 tmpVal = tmpVal | (1 << gpioPin); in GLB_GPIO_OUTPUT_Enable()
2160 tmpVal = tmpVal & ~(1 << gpioPin); in GLB_GPIO_OUTPUT_Disable()
2196 tmpVal = (tmpVal & 0xffff0000); in GLB_GPIO_Set_HZ()
2199 tmpVal = (tmpVal & 0x0000ffff); in GLB_GPIO_Set_HZ()
2382 tmpVal = tmpVal | (1 << gpioPin); in GLB_GPIO_IntMask()
2384 tmpVal = tmpVal & ~(1 << gpioPin); in GLB_GPIO_IntMask()
2411 tmpVal = tmpVal | (1 << gpioPin); in GLB_GPIO_IntClear()
2413 tmpVal = tmpVal & ~(1 << gpioPin); in GLB_GPIO_IntClear()
[all …]
A Dbl602_pds.c104 tmpVal = tmpVal | (1 << 14); in PDS_Reset()
108 tmpVal = tmpVal & ~(1 << 14); in PDS_Reset()
211 tmpVal = tmpVal | (0x1 << 3); in PDS_RAM_Config()
221 tmpVal = tmpVal & ~(0x1 << 3); in PDS_RAM_Config()
303 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); in PDS_IntClear()
307 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); in PDS_IntClear()
311 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); in PDS_IntClear()
610 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL); in PDS_Power_On_PLL()
618 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP); in PDS_Power_On_PLL()
798 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL); in PDS_Power_Off_PLL()
[all …]
A Dbl602_aon.c114 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_Power_On_MBG()
139 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_Power_Off_MBG()
162 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON); in AON_Power_On_XTAL()
242 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON); in AON_Power_Off_XTAL()
266 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON); in AON_Power_On_BG()
466 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_LowPower_Enter_PDS0()
471 tmpVal = tmpVal & (~(1 << 6)); in AON_LowPower_Enter_PDS0()
472 tmpVal = tmpVal & (~(1 << 7)); in AON_LowPower_Enter_PDS0()
495 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_LowPower_Exit_PDS0()
517 tmpVal = tmpVal | ((1 << 6)); in AON_LowPower_Exit_PDS0()
[all …]
A Dbl602_tzc_sec.c92 uint32_t tmpVal; in TZC_Sboot_Set() local
96 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, Val); in TZC_Sboot_Set()
112 uint32_t tmpVal; in TZC_Set_Rom0_R0_Protect() local
128 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_EN, 1); in TZC_Set_Rom0_R0_Protect()
129 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_LOCK, 1); in TZC_Set_Rom0_R0_Protect()
145 uint32_t tmpVal; in TZC_Set_Rom0_R1_Protect() local
161 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_EN, 1); in TZC_Set_Rom0_R1_Protect()
162 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_LOCK, 1); in TZC_Set_Rom0_R1_Protect()
194 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_EN, 1); in TZC_Set_Rom1_R0_Protect()
195 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_LOCK, 1); in TZC_Set_Rom1_R0_Protect()
[all …]
A Dbl602_hbn.c261 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION); in HBN_Enable_Ext()
272 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); in HBN_Enable_Ext()
296 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); in HBN_Reset()
299 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST); in HBN_Reset()
302 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); in HBN_Reset()
372 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_MODE); in HBN_Disable()
391 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN); in HBN_PIR_Enable()
410 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN); in HBN_PIR_Disable()
884 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_SLP); in HBN_Set_HRAM_slp()
973 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K); in HBN_Power_On_RC32K()
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/
A Dbl808_psram_uhs.c182 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_LDO12UHS, 0); in power_up_ldo12uhs()
184 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_LDO12UHS, 1); in power_up_ldo12uhs()
400 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_AF_EN); in Psram_UHS_Init()
409 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_INIT_EN); in Psram_UHS_Init()
429 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ); in PSram_UHS_Read_Reg()
446 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGR_PULSE); in PSram_UHS_Read_Reg()
466 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ); in PSram_UHS_Read_Reg()
529 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ); in PSram_UHS_Write_Reg()
563 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ); in PSram_UHS_Write_Reg()
629 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ); in PSram_UHS_Construct_Cmd()
[all …]
A Dbl808_glb.c1058 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN); in GLB_Power_On_XTAL_And_PLL_CLK()
1364 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB); in GLB_Set_USB_CLK_From_WIFIPLL()
1368 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_USBPLL_RSTB); in GLB_Set_USB_CLK_From_WIFIPLL()
1372 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB); in GLB_Set_USB_CLK_From_WIFIPLL()
2954 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN); in GLB_Set_IR_CLK()
3015 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV); in GLB_IR_LED_Driver_Enable()
3035 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV); in GLB_IR_LED_Driver_Disable()
3162 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); in GLB_Set_SF_CLK()
3229 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN); in GLB_Set_I2C_CLK()
3299 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN); in GLB_Set_SPI_CLK()
[all …]
A Dbl808_tzc_sec.c99 uint32_t tmpVal; in Tzc_Sec_Set_Sboot_Done() local
102 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, 0xf); in Tzc_Sec_Set_Sboot_Done()
108 uint32_t tmpVal; in Tzc_Sec_Set_Master_Group() local
146 uint32_t tmpVal; in Tzc_Sec_Set_Slave_Group() local
192 uint32_t tmpVal; in Tzc_Sec_Set_MM_Slave_Group() local
242 uint32_t tmpVal; in Tzc_Sec_Set_Glb_Ctrl_Group() local
263 uint32_t tmpVal; in Tzc_Sec_Set_MM_Glb_Ctrl_Group() local
284 uint32_t tmpVal; in Tzc_Sec_Set_CPU_Group() local
531 tmpVal = tmpVal & (0xff << (8 * region)); in Tzc_Sec_Flash_Access_Set_Advance()
837 uint32_t tmpVal; in Tzc_Sec_Set_Se_Group() local
[all …]
A Dbl808_aon.c112 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_Power_On_MBG()
134 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_Power_Off_MBG()
154 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON); in AON_Power_On_XTAL()
225 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON); in AON_Power_Off_XTAL()
246 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON); in AON_Power_On_BG()
458 tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_LowPower_Enter_PDS0()
463 tmpVal = tmpVal & (~(1 << 6)); in AON_LowPower_Enter_PDS0()
464 tmpVal = tmpVal & (~(1 << 7)); in AON_LowPower_Enter_PDS0()
484 tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON); in AON_LowPower_Exit_PDS0()
506 tmpVal = tmpVal | ((1 << 6)); in AON_LowPower_Exit_PDS0()
[all …]
A Dbl808_pds.c395 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_MCU1_CLK_EN); in PDS_Set_MCU0_Clock_Enable()
414 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_MCU1_CLK_EN); in PDS_Set_MCU0_Clock_Disable()
448 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_PICO_CLK_EN); in PDS_Set_LP_Clock_Enable()
467 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_PICO_CLK_EN); in PDS_Set_LP_Clock_Disable()
528 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_E902_RTC_RST); in PDS_Reset_LP_RTC()
533 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_E902_RTC_RST); in PDS_Reset_LP_RTC()
538 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_E902_RTC_RST); in PDS_Reset_LP_RTC()
561 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_E902_RTC_EN); in PDS_Set_LP_RTC_CLK()
572 tmpVal = BL_SET_REG_BIT(tmpVal, PDS_E902_RTC_EN); in PDS_Set_LP_RTC_CLK()
574 tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_E902_RTC_EN); in PDS_Set_LP_RTC_CLK()
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A Dbl808_glb_gpio.c122 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE); in GLB_GPIO_Init()
158 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); in GLB_GPIO_Init()
159 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE); in GLB_GPIO_Init()
224 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); in GLB_GPIO_Input_Enable()
270 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); in GLB_GPIO_Input_Disable()
292 tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE); in GLB_GPIO_Output_Enable()
314 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE); in GLB_GPIO_Output_Disable()
337 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE); in GLB_GPIO_Set_HZ()
342 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); in GLB_GPIO_Set_HZ()
343 tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE); in GLB_GPIO_Set_HZ()
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A Dbl808_hbn.c201 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET); in HBN_Enable()
202 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP); in HBN_Enable()
259 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); in HBN_Enable()
281 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); in HBN_Reset()
284 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST); in HBN_Reset()
287 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); in HBN_Reset()
306 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN); in HBN_PIR_Enable()
325 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN); in HBN_PIR_Disable()
886 tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K); in HBN_Power_On_RC32K()
908 tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_RC32K); in HBN_Power_Off_RC32K()
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A Dbl808_uhs_phy.c394 tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL,0x1); in power_up_uhspll()
420 tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x1); in power_up_ldo12uhs()
517 tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_SR,0x2); in set_or_uhs()
518 tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_SR,0x2); in set_or_uhs()
521 tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_SR,0x2); in set_or_uhs()
522 tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_SR,0x2); in set_or_uhs()
537 tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_SR,0x2); in set_or_uhs()
538 tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_SR,0x2); in set_or_uhs()
639 tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x0); in uhs_phy_pwr_down()
1509 tmpVal = (tmpVal >> 16) & 0xF; in reg_write_cal()
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