1 /* 2 * Allwinner SoCs display driver. 3 * 4 * Copyright (C) 2016 Allwinner. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef __DE_DSI_TYPE_H__ 12 #define __DE_DSI_TYPE_H__ 13 14 #include "de_lcd.h" 15 16 /* 17 * Detail information of registers 18 */ 19 union dsi_ctl_reg_t { 20 u32 dwval; 21 struct { 22 u32 dsi_en:1; 23 u32 res0:31; 24 } bits; 25 }; 26 27 union dsi_gint0_reg_t { 28 u32 dwval; 29 struct { 30 u32 dsi_irq_en:16; 31 u32 dsi_irq_flag:16; 32 } bits; 33 }; 34 35 union dsi_gint1_reg_t { 36 u32 dwval; 37 struct { 38 u32 video_line_int_num:13; 39 u32 res0:19; 40 } bits; 41 }; 42 43 union dsi_basic_ctl_reg_t { 44 u32 dwval; 45 struct { 46 u32 video_mode_burst:1; 47 u32 hsa_hse_dis:1; 48 u32 hbp_dis:1; 49 u32 trail_fill:1; 50 u32 trail_inv:4; 51 u32 res0:8; 52 u32 brdy_set:8; 53 u32 brdy_l_sel:3; 54 u32 res1:5; 55 } bits; 56 }; 57 58 union dsi_basic_ctl0_reg_t { 59 u32 dwval; 60 struct { 61 u32 inst_st:1; 62 u32 res0:3; 63 u32 src_sel:2; 64 u32 res1:4; 65 u32 fifo_manual_reset:1; 66 u32 res2:1; 67 u32 fifo_gating:1; 68 u32 res3:3; 69 u32 ecc_en:1; 70 u32 crc_en:1; 71 u32 hs_eotp_en:1; 72 u32 res4:13; 73 } bits; 74 }; 75 76 union dsi_basic_ctl1_reg_t { 77 u32 dwval; 78 struct { 79 u32 dsi_mode:1; 80 u32 video_frame_start:1; 81 u32 video_precision_mode_align:1; 82 u32 res0:1; 83 u32 video_start_delay:13; 84 u32 res1:15; 85 } bits; 86 }; 87 88 union dsi_basic_size0_reg_t { 89 u32 dwval; 90 struct { 91 u32 vsa:12; 92 u32 res0:4; 93 u32 vbp:12; 94 u32 res1:4; 95 } bits; 96 }; 97 98 union dsi_basic_size1_reg_t { 99 u32 dwval; 100 struct { 101 u32 vact:12; 102 u32 res0:4; 103 u32 vt:13; 104 u32 res1:3; 105 } bits; 106 }; 107 108 union dsi_basic_inst0_reg_t { 109 u32 dwval; 110 struct { 111 u32 lane_den:4; 112 u32 lane_cen:1; 113 u32 res0:11; 114 u32 trans_start_condition:4; 115 u32 trans_packet:4; 116 u32 escape_enrty:4; 117 u32 instru_mode:4; 118 } bits; 119 }; 120 121 union dsi_basic_inst1_reg_t { 122 u32 dwval; 123 struct { 124 u32 inst0_sel:4; 125 u32 inst1_sel:4; 126 u32 inst2_sel:4; 127 u32 inst3_sel:4; 128 u32 inst4_sel:4; 129 u32 inst5_sel:4; 130 u32 inst6_sel:4; 131 u32 inst7_sel:4; 132 } bits; 133 }; 134 135 union dsi_basic_inst2_reg_t { 136 u32 dwval; 137 struct { 138 u32 loop_n0:12; 139 u32 res0:4; 140 u32 loop_n1:12; 141 u32 res1:4; 142 } bits; 143 }; 144 145 union dsi_basic_inst3_reg_t { 146 u32 dwval; 147 struct { 148 u32 inst0_jump:4; 149 u32 inst1_jump:4; 150 u32 inst2_jump:4; 151 u32 inst3_jump:4; 152 u32 inst4_jump:4; 153 u32 inst5_jump:4; 154 u32 inst6_jump:4; 155 u32 inst7_jump:4; 156 } bits; 157 }; 158 159 union dsi_basic_inst4_reg_t { 160 u32 dwval; 161 struct { 162 u32 jump_cfg_num:16; 163 u32 jump_cfg_point:4; 164 u32 jump_cfg_to:4; 165 u32 res0:4; 166 u32 jump_cfg_en:1; 167 u32 res1:3; 168 } bits; 169 }; 170 171 union dsi_basic_tran0_reg_t { 172 u32 dwval; 173 struct { 174 u32 trans_start_set:13; 175 u32 res0:19; 176 } bits; 177 }; 178 179 union dsi_basic_tran1_reg_t { 180 u32 dwval; 181 struct { 182 u32 trans_size:16; 183 u32 res0:12; 184 u32 trans_end_condition:1; 185 u32 res1:3; 186 } bits; 187 }; 188 189 union dsi_basic_tran2_reg_t { 190 u32 dwval; 191 struct { 192 u32 trans_cycle_set:16; 193 u32 res0:16; 194 } bits; 195 }; 196 197 union dsi_basic_tran3_reg_t { 198 u32 dwval; 199 struct { 200 u32 trans_blank_set:16; 201 u32 res0:16; 202 } bits; 203 }; 204 205 union dsi_basic_tran4_reg_t { 206 u32 dwval; 207 struct { 208 u32 hs_zero_reduce_set:16; 209 u32 res0:16; 210 } bits; 211 }; 212 213 union dsi_basic_tran5_reg_t { 214 u32 dwval; 215 struct { 216 u32 drq_set:10; 217 u32 res0:18; 218 u32 drq_mode:1; 219 u32 res1:3; 220 } bits; 221 }; 222 223 union dsi_pixel_ctl0_reg_t { 224 u32 dwval; 225 struct { 226 u32 pixel_format:4; 227 u32 pixel_endian:1; 228 u32 res0:11; 229 u32 pd_plug_dis:1; 230 u32 res1:15; 231 } bits; 232 }; 233 234 union dsi_pixel_ctl1_reg_t { 235 u32 dwval; 236 struct { 237 u32 res0; 238 } bits; 239 }; 240 241 union dsi_pixel_ph_reg_t { 242 u32 dwval; 243 struct { 244 u32 dt:6; 245 u32 vc:2; 246 u32 wc:16; 247 u32 ecc:8; 248 } bits; 249 }; 250 251 union dsi_pixel_pd_reg_t { 252 u32 dwval; 253 struct { 254 u32 pd_tran0:8; 255 u32 res0:8; 256 u32 pd_trann:8; 257 u32 res1:8; 258 } bits; 259 }; 260 261 union dsi_pixel_pf0_reg_t { 262 u32 dwval; 263 struct { 264 u32 crc_force:16; 265 u32 res0:16; 266 } bits; 267 }; 268 269 union dsi_pixel_pf1_reg_t { 270 u32 dwval; 271 struct { 272 u32 crc_init_line0:16; 273 u32 crc_init_linen:16; 274 } bits; 275 }; 276 277 union dsi_short_pkg_reg_t { 278 u32 dwval; 279 struct { 280 u32 dt:6; 281 u32 vc:2; 282 u32 d0:8; 283 u32 d1:8; 284 u32 ecc:8; 285 } bits; 286 }; 287 288 union dsi_blk_pkg0_reg_t { 289 u32 dwval; 290 struct { 291 u32 dt:6; 292 u32 vc:2; 293 u32 wc:16; 294 u32 ecc:8; 295 } bits; 296 }; 297 298 union dsi_blk_pkg1_reg_t { 299 u32 dwval; 300 struct { 301 u32 pd:8; 302 u32 res0:8; 303 u32 pf:16; 304 } bits; 305 }; 306 307 union dsi_burst_line_reg_t { 308 u32 dwval; 309 struct { 310 u32 line_num:16; 311 u32 line_syncpoint:16; 312 } bits; 313 }; 314 315 union dsi_burst_drq_reg_t { 316 u32 dwval; 317 struct { 318 u32 drq_edge0:16; 319 u32 drq_edge1:16; 320 } bits; 321 }; 322 323 union dsi_cmd_ctl_reg_t { 324 u32 dwval; 325 struct { 326 u32 tx_size:8; 327 u32 tx_status:1; 328 u32 tx_flag:1; 329 u32 res0:6; 330 u32 rx_size:5; 331 u32 res1:3; 332 u32 rx_status:1; 333 u32 rx_flag:1; 334 u32 rx_overflow:1; 335 u32 res2:5; 336 } bits; 337 }; 338 339 union dsi_cmd_data_reg_t { 340 u32 dwval; 341 struct { 342 u32 byte0:8; 343 u32 byte1:8; 344 u32 byte2:8; 345 u32 byte3:8; 346 } bits; 347 }; 348 349 union dsi_debug0_reg_t { 350 u32 dwval; 351 struct { 352 u32 video_curr_line:13; 353 u32 res0:19; 354 } bits; 355 }; 356 357 union dsi_debug1_reg_t { 358 u32 dwval; 359 struct { 360 u32 video_curr_lp2hs:16; 361 u32 res0:16; 362 } bits; 363 }; 364 365 union dsi_debug2_reg_t { 366 u32 dwval; 367 struct { 368 u32 trans_low_flag:1; 369 u32 trans_fast_flag:1; 370 u32 res0:2; 371 u32 curr_loop_num:16; 372 u32 curr_instru_num:3; 373 u32 res1:1; 374 u32 instru_unknown_flag:8; 375 } bits; 376 }; 377 378 union dsi_debug3_reg_t { 379 u32 dwval; 380 struct { 381 u32 res0:16; 382 u32 curr_fifo_num:16; 383 } bits; 384 }; 385 386 union dsi_debug4_reg_t { 387 u32 dwval; 388 struct { 389 u32 test_data:24; 390 u32 res0:4; 391 u32 dsi_fifo_bist_en:1; 392 u32 res1:3; 393 } bits; 394 }; 395 396 union dsi_reservd_reg_t { 397 u32 dwval; 398 struct { 399 u32 res0; 400 } bits; 401 }; 402 403 struct __de_dsi_dev_t { 404 /* 0x00 - 0x0c */ 405 union dsi_ctl_reg_t dsi_gctl; 406 union dsi_gint0_reg_t dsi_gint0; 407 union dsi_gint1_reg_t dsi_gint1; 408 union dsi_basic_ctl_reg_t dsi_basic_ctl; 409 /* 0x10 - 0x1c */ 410 union dsi_basic_ctl0_reg_t dsi_basic_ctl0; 411 union dsi_basic_ctl1_reg_t dsi_basic_ctl1; 412 union dsi_basic_size0_reg_t dsi_basic_size0; 413 union dsi_basic_size1_reg_t dsi_basic_size1; 414 /* 0x20 - 0x3c */ 415 union dsi_basic_inst0_reg_t dsi_inst_func[8]; 416 /* 0x40 - 0x5c */ 417 union dsi_basic_inst1_reg_t dsi_inst_loop_sel; 418 union dsi_basic_inst2_reg_t dsi_inst_loop_num; 419 union dsi_basic_inst3_reg_t dsi_inst_jump_sel; 420 union dsi_basic_inst4_reg_t dsi_inst_jump_cfg[2]; 421 union dsi_basic_inst2_reg_t dsi_inst_loop_num2; 422 union dsi_reservd_reg_t dsi_reg058[2]; 423 /* 0x60 - 0x6c */ 424 union dsi_basic_tran0_reg_t dsi_trans_start; 425 union dsi_reservd_reg_t dsi_reg064[3]; 426 /* 0x70 - 0x7c */ 427 union dsi_reservd_reg_t dsi_reg070[2]; 428 union dsi_basic_tran4_reg_t dsi_trans_zero; 429 union dsi_basic_tran5_reg_t dsi_tcon_drq; 430 /* 0x80 - 0x8c */ 431 union dsi_pixel_ctl0_reg_t dsi_pixel_ctl0; 432 union dsi_pixel_ctl1_reg_t dsi_pixel_ctl1; 433 union dsi_reservd_reg_t dsi_reg088[2]; 434 /* 0x90 - 0x9c */ 435 union dsi_pixel_ph_reg_t dsi_pixel_ph; 436 union dsi_pixel_pd_reg_t dsi_pixel_pd; 437 union dsi_pixel_pf0_reg_t dsi_pixel_pf0; 438 union dsi_pixel_pf1_reg_t dsi_pixel_pf1; 439 /* 0xa0 - 0xac */ 440 union dsi_reservd_reg_t dsi_reg0a0[4]; 441 /* 0xb0 - 0xbc */ 442 union dsi_short_pkg_reg_t dsi_sync_hss; 443 union dsi_short_pkg_reg_t dsi_sync_hse; 444 union dsi_short_pkg_reg_t dsi_sync_vss; 445 union dsi_short_pkg_reg_t dsi_sync_vse; 446 /* 0xc0 - 0xcc */ 447 union dsi_blk_pkg0_reg_t dsi_blk_hsa0; 448 union dsi_blk_pkg1_reg_t dsi_blk_hsa1; 449 union dsi_blk_pkg0_reg_t dsi_blk_hbp0; 450 union dsi_blk_pkg1_reg_t dsi_blk_hbp1; 451 /* 0xd0 - 0xdc */ 452 union dsi_blk_pkg0_reg_t dsi_blk_hfp0; 453 union dsi_blk_pkg1_reg_t dsi_blk_hfp1; 454 union dsi_reservd_reg_t dsi_reg0d8[2]; 455 /* 0xe0 - 0xec */ 456 union dsi_blk_pkg0_reg_t dsi_blk_hblk0; 457 union dsi_blk_pkg1_reg_t dsi_blk_hblk1; 458 union dsi_blk_pkg0_reg_t dsi_blk_vblk0; 459 union dsi_blk_pkg1_reg_t dsi_blk_vblk1; 460 /* 0xf0 - 0x1fc */ 461 union dsi_burst_line_reg_t dsi_burst_line; 462 union dsi_burst_drq_reg_t dsi_burst_drq; 463 union dsi_reservd_reg_t dsi_reg0f0[66]; 464 /* 0x200 - 0x23c */ 465 union dsi_cmd_ctl_reg_t dsi_cmd_ctl; 466 union dsi_reservd_reg_t dsi_reg204[15]; 467 /* 0x240 - 0x2dc */ 468 union dsi_cmd_data_reg_t dsi_cmd_rx[8]; 469 union dsi_reservd_reg_t dsi_reg260[32]; 470 /* 0x2e0 - 0x2ec */ 471 union dsi_debug0_reg_t dsi_debug_video0; 472 union dsi_debug1_reg_t dsi_debug_video1; 473 union dsi_reservd_reg_t dsi_reg2e8[2]; 474 /* 0x2f0 - 0x2fc */ 475 union dsi_debug2_reg_t dsi_debug_inst; 476 union dsi_debug3_reg_t dsi_debug_fifo; 477 union dsi_debug4_reg_t dsi_debug_data; 478 union dsi_reservd_reg_t dsi_reg2fc; 479 /* 0x300 - 0x3fc */ 480 union dsi_cmd_data_reg_t dsi_cmd_tx[64]; 481 }; 482 483 union dphy_ctl_reg_t { 484 u32 dwval; 485 struct { 486 u32 module_en:1; 487 u32 res0:3; 488 u32 lane_num:2; 489 u32 res1:26; 490 } bits; 491 }; 492 493 union dphy_tx_ctl_reg_t { 494 u32 dwval; 495 struct { 496 u32 tx_d0_force:1; 497 u32 tx_d1_force:1; 498 u32 tx_d2_force:1; 499 u32 tx_d3_force:1; 500 u32 tx_clk_force:1; 501 u32 res0:3; 502 u32 lptx_endian:1; 503 u32 hstx_endian:1; 504 u32 lptx_8b9b_en:1; 505 u32 hstx_8b9b_en:1; 506 u32 force_lp11:1; 507 u32 res1:3; 508 u32 ulpstx_data0_exit:1; 509 u32 ulpstx_data1_exit:1; 510 u32 ulpstx_data2_exit:1; 511 u32 ulpstx_data3_exit:1; 512 u32 ulpstx_clk_exit:1; 513 u32 res2:3; 514 u32 hstx_data_exit:1; 515 u32 hstx_clk_exit:1; 516 u32 res3:2; 517 u32 hstx_clk_cont:1; 518 u32 ulpstx_enter:1; 519 u32 res4:2; 520 } bits; 521 }; 522 523 union dphy_rx_ctl_reg_t { 524 u32 dwval; 525 struct { 526 u32 res0:8; 527 u32 lprx_endian:1; 528 u32 hsrx_endian:1; 529 u32 lprx_8b9b_en:1; 530 u32 hsrx_8b9b_en:1; 531 u32 hsrx_sync:1; 532 u32 res1:3; 533 u32 lprx_trnd_mask:4; 534 u32 rx_d0_force:1; 535 u32 rx_d1_force:1; 536 u32 rx_d2_force:1; 537 u32 rx_d3_force:1; 538 u32 rx_clk_force:1; 539 u32 res2:6; 540 u32 dbc_en:1; 541 } bits; 542 }; 543 544 union dphy_tx_time0_reg_t { 545 u32 dwval; 546 struct { 547 u32 lpx_tm_set:8; 548 u32 dterm_set:8; 549 u32 hs_pre_set:8; 550 u32 hs_trail_set:8; 551 } bits; 552 }; 553 554 union dphy_tx_time1_reg_t { 555 u32 dwval; 556 struct { 557 u32 ck_prep_set:8; 558 u32 ck_zero_set:8; 559 u32 ck_pre_set:8; 560 u32 ck_post_set:8; 561 } bits; 562 }; 563 564 union dphy_tx_time2_reg_t { 565 u32 dwval; 566 struct { 567 u32 ck_trail_set:8; 568 u32 hs_dly_set:16; 569 u32 res0:4; 570 u32 hs_dly_mode:1; 571 u32 res1:3; 572 } bits; 573 }; 574 575 union dphy_tx_time3_reg_t { 576 u32 dwval; 577 struct { 578 u32 lptx_ulps_exit_set:20; 579 u32 res0:12; 580 } bits; 581 }; 582 583 union dphy_tx_time4_reg_t { 584 u32 dwval; 585 struct { 586 u32 hstx_ana0_set:8; 587 u32 hstx_ana1_set:8; 588 u32 res0:16; 589 } bits; 590 }; 591 592 union dphy_rx_time0_reg_t { 593 u32 dwval; 594 struct { 595 u32 lprx_to_en:1; 596 u32 freq_cnt_en:1; 597 u32 res0:2; 598 u32 hsrx_clk_miss_en:1; 599 u32 hsrx_sync_err_to_en:1; 600 u32 res1:2; 601 u32 lprx_to:8; 602 u32 hsrx_clk_miss:8; 603 u32 hsrx_sync_err_to:8; 604 } bits; 605 }; 606 607 union dphy_rx_time1_reg_t { 608 u32 dwval; 609 struct { 610 u32 lprx_ulps_wp:20; 611 u32 rx_dly:12; 612 } bits; 613 }; 614 615 union dphy_rx_time2_reg_t { 616 u32 dwval; 617 struct { 618 u32 hsrx_ana0_set:8; 619 u32 hsrx_ana1_set:8; 620 u32 res0:16; 621 } bits; 622 }; 623 624 union dphy_rx_time3_reg_t { 625 u32 dwval; 626 struct { 627 u32 freq_cnt:16; 628 u32 res0:8; 629 u32 lprst_dly:8; 630 } bits; 631 }; 632 633 union dphy_ana0_reg_t { 634 u32 dwval; 635 struct { 636 u32 reg_selsck:1; 637 u32 reg_rsd:1; 638 u32 reg_sfb:2; 639 u32 reg_plr:4; 640 u32 reg_den:4; 641 u32 reg_slv:3; 642 u32 reg_sdiv2:1; 643 u32 reg_srxck:4; 644 u32 reg_srxdt:4; 645 u32 reg_dmpd:4; 646 u32 reg_dmpc:1; 647 u32 reg_pwenc:1; 648 u32 reg_pwend:1; 649 u32 reg_pws:1; 650 } bits; 651 }; 652 653 union dphy_ana1_reg_t { 654 u32 dwval; 655 struct { 656 u32 reg_stxck:1; 657 u32 res0:3; 658 u32 reg_svdl0:4; 659 u32 reg_svdl1:4; 660 u32 reg_svdl2:4; 661 u32 reg_svdl3:4; 662 u32 reg_svdlc:4; 663 u32 reg_svtt:4; 664 u32 reg_csmps:2; 665 u32 res1:1; 666 u32 reg_vttmode:1; 667 } bits; 668 }; 669 670 union dphy_ana2_reg_t { 671 u32 dwval; 672 struct { 673 u32 ana_cpu_en:1; 674 u32 enib:1; 675 u32 enrvs:1; 676 u32 res0:1; 677 u32 enck_cpu:1; 678 u32 entxc_cpu:1; 679 u32 enckq_cpu:1; 680 u32 res1:1; 681 u32 entx_cpu:4; 682 u32 res2:1; 683 u32 entermc_cpu:1; 684 u32 enrxc_cpu:1; 685 u32 res3:1; 686 u32 enterm_cpu:4; 687 u32 enrx_cpu:4; 688 u32 enp2s_cpu:4; 689 u32 res4:4; 690 } bits; 691 }; 692 693 union dphy_ana3_reg_t { 694 u32 dwval; 695 struct { 696 u32 enlptx_cpu:4; 697 u32 enlprx_cpu:4; 698 u32 enlpcd_cpu:4; 699 u32 enlprxc_cpu:1; 700 u32 enlptxc_cpu:1; 701 u32 enlpcdc_cpu:1; 702 u32 res0:1; 703 u32 entest:1; 704 u32 enckdbg:1; 705 u32 enldor:1; 706 u32 res1:5; 707 u32 enldod:1; 708 u32 enldoc:1; 709 u32 endiv:1; 710 u32 envttc:1; 711 u32 envttd:4; 712 } bits; 713 }; 714 715 union dphy_ana4_reg_t { 716 u32 dwval; 717 struct { 718 u32 reg_txpusd:2; 719 u32 reg_txpusc:2; 720 u32 reg_txdnsd:2; 721 u32 reg_txdnsc:2; 722 u32 reg_tmsd:2; 723 u32 reg_tmsc:2; 724 u32 reg_ckdv:5; 725 u32 reg_vtt_set:3; 726 u32 reg_dmplvd:4; 727 u32 reg_dmplvc:1; 728 u32 reg_ib:2; 729 u32 res4:1; 730 u32 reg_comtest:2; 731 u32 en_comtest:1; 732 u32 en_mipi:1; 733 734 } bits; 735 }; 736 737 union dphy_int_en0_reg_t { 738 u32 dwval; 739 struct { 740 u32 sot_d0_int:1; 741 u32 sot_d1_int:1; 742 u32 sot_d2_int:1; 743 u32 sot_d3_int:1; 744 u32 sot_err_d0_int:1; 745 u32 sot_err_d1_int:1; 746 u32 sot_err_d2_int:1; 747 u32 sot_err_d3_int:1; 748 u32 sot_sync_err_d0_int:1; 749 u32 sot_sync_err_d1_int:1; 750 u32 sot_sync_err_d2_int:1; 751 u32 sot_sync_err_d3_int:1; 752 u32 rx_alg_err_d0_int:1; 753 u32 rx_alg_err_d1_int:1; 754 u32 rx_alg_err_d2_int:1; 755 u32 rx_alg_err_d3_int:1; 756 u32 res0:6; 757 u32 cd_lp0_err_clk_int:1; 758 u32 cd_lp1_err_clk_int:1; 759 u32 cd_lp0_err_d0_int:1; 760 u32 cd_lp1_err_d0_int:1; 761 u32 cd_lp0_err_d1_int:1; 762 u32 cd_lp1_err_d1_int:1; 763 u32 cd_lp0_err_d2_int:1; 764 u32 cd_lp1_err_d2_int:1; 765 u32 cd_lp0_err_d3_int:1; 766 u32 cd_lp1_err_d3_int:1; 767 } bits; 768 }; 769 770 union dphy_int_en1_reg_t { 771 u32 dwval; 772 struct { 773 u32 ulps_d0_int:1; 774 u32 ulps_d1_int:1; 775 u32 ulps_d2_int:1; 776 u32 ulps_d3_int:1; 777 u32 ulps_wp_d0_int:1; 778 u32 ulps_wp_d1_int:1; 779 u32 ulps_wp_d2_int:1; 780 u32 ulps_wp_d3_int:1; 781 u32 ulps_clk_int:1; 782 u32 ulps_wp_clk_int:1; 783 u32 res0:2; 784 u32 lpdt_d0_int:1; 785 u32 rx_trnd_d0_int:1; 786 u32 tx_trnd_err_d0_int:1; 787 u32 undef1_d0_int:1; 788 u32 undef2_d0_int:1; 789 u32 undef3_d0_int:1; 790 u32 undef4_d0_int:1; 791 u32 undef5_d0_int:1; 792 u32 rst_d0_int:1; 793 u32 rst_d1_int:1; 794 u32 rst_d2_int:1; 795 u32 rst_d3_int:1; 796 u32 esc_cmd_err_d0_int:1; 797 u32 esc_cmd_err_d1_int:1; 798 u32 esc_cmd_err_d2_int:1; 799 u32 esc_cmd_err_d3_int:1; 800 u32 false_ctl_d0_int:1; 801 u32 false_ctl_d1_int:1; 802 u32 false_ctl_d2_int:1; 803 u32 false_ctl_d3_int:1; 804 } bits; 805 }; 806 807 union dphy_int_en2_reg_t { 808 u32 dwval; 809 struct { 810 u32 res0; 811 } bits; 812 }; 813 814 union dphy_int_pd0_reg_t { 815 u32 dwval; 816 struct { 817 u32 sot_d0_pd:1; 818 u32 sot_d1_pd:1; 819 u32 sot_d2_pd:1; 820 u32 sot_d3_pd:1; 821 u32 sot_err_d0_pd:1; 822 u32 sot_err_d1_pd:1; 823 u32 sot_err_d2_pd:1; 824 u32 sot_err_d3_pd:1; 825 u32 sot_sync_err_d0_pd:1; 826 u32 sot_sync_err_d1_pd:1; 827 u32 sot_sync_err_d2_pd:1; 828 u32 sot_sync_err_d3_pd:1; 829 u32 rx_alg_err_d0_pd:1; 830 u32 rx_alg_err_d1_pd:1; 831 u32 rx_alg_err_d2_pd:1; 832 u32 rx_alg_err_d3_pd:1; 833 u32 res0:6; 834 u32 cd_lp0_err_clk_pd:1; 835 u32 cd_lp1_err_clk_pd:1; 836 u32 cd_lp0_err_d1_pd:1; 837 u32 cd_lp1_err_d1_pd:1; 838 u32 cd_lp0_err_d0_pd:1; 839 u32 cd_lp1_err_d0_pd:1; 840 u32 cd_lp0_err_d2_pd:1; 841 u32 cd_lp1_err_d2_pd:1; 842 u32 cd_lp0_err_d3_pd:1; 843 u32 cd_lp1_err_d3_pd:1; 844 } bits; 845 }; 846 847 union dphy_int_pd1_reg_t { 848 u32 dwval; 849 struct { 850 u32 ulps_d0_pd:1; 851 u32 ulps_d1_pd:1; 852 u32 ulps_d2_pd:1; 853 u32 ulps_d3_pd:1; 854 u32 ulps_wp_d0_pd:1; 855 u32 ulps_wp_d1_pd:1; 856 u32 ulps_wp_d2_pd:1; 857 u32 ulps_wp_d3_pd:1; 858 u32 ulps_clk_pd:1; 859 u32 ulps_wp_clk_pd:1; 860 u32 res0:2; 861 u32 lpdt_d0_pd:1; 862 u32 rx_trnd_d0_pd:1; 863 u32 tx_trnd_err_d0_pd:1; 864 u32 undef1_d0_pd:1; 865 u32 undef2_d0_pd:1; 866 u32 undef3_d0_pd:1; 867 u32 undef4_d0_pd:1; 868 u32 undef5_d0_pd:1; 869 u32 rst_d0_pd:1; 870 u32 rst_d1_pd:1; 871 u32 rst_d2_pd:1; 872 u32 rst_d3_pd:1; 873 u32 esc_cmd_err_d0_pd:1; 874 u32 esc_cmd_err_d1_pd:1; 875 u32 esc_cmd_err_d2_pd:1; 876 u32 esc_cmd_err_d3_pd:1; 877 u32 false_ctl_d0_pd:1; 878 u32 false_ctl_d1_pd:1; 879 u32 false_ctl_d2_pd:1; 880 u32 false_ctl_d3_pd:1; 881 } bits; 882 }; 883 884 union dphy_int_pd2_reg_t { 885 u32 dwval; 886 struct { 887 u32 res0; 888 } bits; 889 }; 890 891 union dphy_dbg0_reg_t { 892 u32 dwval; 893 struct { 894 u32 lptx_sta_d0:3; 895 u32 res0:1; 896 u32 lptx_sta_d1:3; 897 u32 res1:1; 898 u32 lptx_sta_d2:3; 899 u32 res2:1; 900 u32 lptx_sta_d3:3; 901 u32 res3:1; 902 u32 lptx_sta_clk:3; 903 u32 res4:9; 904 u32 direction:1; 905 u32 res5:3; 906 } bits; 907 }; 908 909 union dphy_dbg1_reg_t { 910 u32 dwval; 911 struct { 912 u32 lptx_dbg_en:1; 913 u32 hstx_dbg_en:1; 914 u32 res0:2; 915 u32 lptx_set_d0:2; 916 u32 lptx_set_d1:2; 917 u32 lptx_set_d2:2; 918 u32 lptx_set_d3:2; 919 u32 lptx_set_ck:2; 920 u32 res1:18; 921 } bits; 922 }; 923 924 union dphy_dbg2_reg_t { 925 u32 dwval; 926 struct { 927 u32 hstx_data; 928 } bits; 929 }; 930 931 union dphy_dbg3_reg_t { 932 u32 dwval; 933 struct { 934 u32 lprx_sta_d0:4; 935 u32 lprx_sta_d1:4; 936 u32 lprx_sta_d2:4; 937 u32 lprx_sta_d3:4; 938 u32 lprx_sta_clk:4; 939 u32 res0:12; 940 } bits; 941 }; 942 943 union dphy_dbg4_reg_t { 944 u32 dwval; 945 struct { 946 u32 lprx_phy_d0:2; 947 u32 lprx_phy_d1:2; 948 u32 lprx_phy_d2:2; 949 u32 lprx_phy_d3:2; 950 u32 lprx_phy_clk:2; 951 u32 res0:6; 952 u32 lpcd_phy_d0:2; 953 u32 lpcd_phy_d1:2; 954 u32 lpcd_phy_d2:2; 955 u32 lpcd_phy_d3:2; 956 u32 lpcd_phy_clk:2; 957 u32 res1:6; 958 } bits; 959 }; 960 961 union dphy_dbg5_reg_t { 962 u32 dwval; 963 struct { 964 u32 hsrx_data; 965 } bits; 966 }; 967 968 union dphy_reservd_reg_t { 969 u32 dwval; 970 struct { 971 u32 res0; 972 } bits; 973 }; 974 975 976 union dphy_tx_skew_reg0_t { 977 __u32 dwavl; 978 struct { 979 __u32 reg_skewcal_sync : 8 ; // default: 0; 980 __u32 reg_skewcal : 8 ; // default: 0; 981 __u32 skewcal_trail_set : 8 ; // default: 0; 982 __u32 skewcal_zero_set : 8 ; // default: 0; 983 } bits; 984 }; 985 986 union dphy_tx_skew_reg1_t { 987 __u32 dwval; 988 struct { 989 __u32 skewcal_init_set : 16 ; // default: 0; 990 __u32 skewcal_pedic_set : 8 ; // default: 0; 991 __u32 skewcal_sync_set : 8 ; // default: 0; 992 } bits; 993 }; 994 995 union dphy_tx_skew_reg2_t { 996 __u32 dwval; 997 struct { 998 __u32 skewcal_prepare_lp00 : 8 ; //default: 0; 999 __u32 skewcal_trail_inv : 1 ; //default: 0; 1000 __u32 en_skewcal_perdic : 1 ; //default: 0; 1001 __u32 en_skewcal_init : 1 ; //default: 0; 1002 __u32 res0 : 21 ; //default: 0; 1003 } bits; 1004 }; 1005 1006 union dphy_pll_reg0_t { 1007 __u32 dwval; 1008 struct { 1009 __u32 m1 : 4 ; //default: 0x3; 1010 __u32 m0 : 2 ; //default: 0; 1011 __u32 tdiv : 1 ; //default: 0; 1012 __u32 ndet : 1 ; //default: 0x1; 1013 __u32 n : 8 ; //default: 0x32; 1014 __u32 p : 4 ; //default: 0; 1015 __u32 pll_en : 1 ; //default: 0x1; 1016 __u32 en_lvs : 1 ; //default: 0x1; 1017 __u32 ldo_en : 1 ; //default: 0x1; 1018 __u32 cp36_en : 1 ; //default: 0x1; 1019 __u32 res0 : 8 ; //default: 0; 1020 } bits; 1021 }; 1022 1023 union dphy_pll_reg1_t { 1024 __u32 dwval; 1025 struct { 1026 __u32 test_en : 1 ; //default: 0x1; 1027 __u32 atest_sel : 2 ; //default: 0; 1028 __u32 icp_sel : 2 ; //default: 0; 1029 __u32 lpf_sw : 1 ; //default: 0; 1030 __u32 vsetd : 3 ; //default: 0x2; 1031 __u32 vseta : 3 ; //default: 0x2; 1032 __u32 lockdet_en : 1 ; //default: 0; 1033 __u32 lockmdsel : 1 ; //default: 0; 1034 __u32 unlock_mdsel : 2 ; //default: 0; 1035 __u32 res0 : 16 ; //default: 0; 1036 } bits; 1037 }; 1038 1039 union dphy_pll_reg2_t { 1040 __u32 dwval; 1041 struct { 1042 __u32 frac : 12 ; //default: 0x800; 1043 __u32 ss_int : 8 ; //default: 0x32; 1044 __u32 ss_frac : 9 ; //default: 0; 1045 __u32 ss_en : 1 ; //default: 0; 1046 __u32 ff_en : 1 ; //default: 0; 1047 __u32 sdm_en : 1 ; //default: 0x1; 1048 } bits; 1049 }; 1050 1051 union combo_phy_reg0_t { 1052 __u32 dwval; 1053 struct { 1054 __u32 en_cp : 1 ; //default: 0; 1055 __u32 en_comboldo : 1 ; //default: 0; 1056 __u32 en_lvds : 1 ; //default: 0; 1057 __u32 en_mipi : 1 ; //default: 0; 1058 __u32 en_test_0p8 : 1 ; //default: 0; 1059 __u32 en_test_comboldo : 1 ; //default: 0; 1060 __u32 res0 : 26; //default: 0; 1061 } bits; 1062 }; 1063 1064 union combo_phy_reg1_t { 1065 __u32 dwval; 1066 struct { 1067 __u32 reg_vref0p8 : 3 ; //default: 0; 1068 __u32 res0 : 1 ; //default: 0; 1069 __u32 reg_vref1p6 : 3 ; //default: 0; 1070 __u32 res1 : 25; //default: 0; 1071 } bits; 1072 }; 1073 1074 union combo_phy_reg2_t { 1075 __u32 dwval; 1076 struct { 1077 __u32 hs_stop_dly : 8 ; //default: 0; 1078 __u32 res0 : 24; //default: 0; 1079 } bits; 1080 }; 1081 1082 /* dphy register define */ 1083 struct __de_dsi_dphy_dev_t { 1084 /* 0x00 - 0x0c */ 1085 union dphy_ctl_reg_t dphy_gctl; 1086 union dphy_tx_ctl_reg_t dphy_tx_ctl; 1087 union dphy_rx_ctl_reg_t dphy_rx_ctl; 1088 union dphy_reservd_reg_t dphy_reg00c; 1089 /* 0x10 - 0x1c */ 1090 union dphy_tx_time0_reg_t dphy_tx_time0; 1091 union dphy_tx_time1_reg_t dphy_tx_time1; 1092 union dphy_tx_time2_reg_t dphy_tx_time2; 1093 union dphy_tx_time3_reg_t dphy_tx_time3; 1094 /* 0x20 - 0x2c */ 1095 union dphy_tx_time4_reg_t dphy_tx_time4; 1096 union dphy_reservd_reg_t dphy_reg024[3]; 1097 /* 0x30 - 0x3c */ 1098 union dphy_rx_time0_reg_t dphy_rx_time0; 1099 union dphy_rx_time1_reg_t dphy_rx_time1; 1100 union dphy_rx_time2_reg_t dphy_rx_time2; 1101 union dphy_reservd_reg_t dphy_reg03c; 1102 /* 0x40 - 0x4c */ 1103 union dphy_rx_time3_reg_t dphy_rx_time3; 1104 union dphy_reservd_reg_t dphy_reg044[2]; 1105 union dphy_ana0_reg_t dphy_ana0; 1106 /* 0x50 - 0x5c */ 1107 union dphy_ana1_reg_t dphy_ana1; 1108 union dphy_ana2_reg_t dphy_ana2; 1109 union dphy_ana3_reg_t dphy_ana3; 1110 union dphy_ana4_reg_t dphy_ana4; 1111 /* 0x60 - 0x6c */ 1112 union dphy_int_en0_reg_t dphy_int_en0; 1113 union dphy_int_en1_reg_t dphy_int_en1; 1114 union dphy_int_en2_reg_t dphy_int_en2; 1115 union dphy_reservd_reg_t dphy_reg06c; 1116 /* 0x70 - 0x7c */ 1117 union dphy_int_pd0_reg_t dphy_int_pd0; 1118 union dphy_int_pd1_reg_t dphy_int_pd1; 1119 union dphy_int_pd2_reg_t dphy_int_pd2; 1120 union dphy_reservd_reg_t dphy_reg07c; 1121 /* 0x80 - 0xdc */ 1122 union dphy_reservd_reg_t dphy_reg080[24]; 1123 /* 0xe0 - 0xec */ 1124 union dphy_dbg0_reg_t dphy_dbg0; 1125 union dphy_dbg1_reg_t dphy_dbg1; 1126 union dphy_dbg2_reg_t dphy_dbg2; 1127 union dphy_dbg3_reg_t dphy_dbg3; 1128 /* 0xf0 - 0xfc */ 1129 union dphy_dbg4_reg_t dphy_dbg4; 1130 union dphy_dbg5_reg_t dphy_dbg5; 1131 union dphy_tx_skew_reg0_t dphy_tx_skew_reg0; /*0xf8 */ 1132 union dphy_tx_skew_reg1_t dphy_tx_skew_reg1; /*0xfc */ 1133 union dphy_tx_skew_reg2_t dphy_tx_skew_reg2; /*0x100 */ 1134 union dphy_pll_reg0_t dphy_pll_reg0; /*0x104 */ 1135 union dphy_pll_reg1_t dphy_pll_reg1; /*0x108 */ 1136 union dphy_pll_reg2_t dphy_pll_reg2; /*0x10c */ 1137 union combo_phy_reg0_t combo_phy_reg0; /*0x110 */ 1138 union combo_phy_reg1_t combo_phy_reg1; /*0x114 */ 1139 union combo_phy_reg2_t combo_phy_reg2; /*0x118 */ 1140 }; 1141 1142 union dsi_ph_t { 1143 struct { 1144 u32 byte012:24; 1145 u32 byte3:8; 1146 } bytes; 1147 struct { 1148 u32 bit00:1; 1149 u32 bit01:1; 1150 u32 bit02:1; 1151 u32 bit03:1; 1152 u32 bit04:1; 1153 u32 bit05:1; 1154 u32 bit06:1; 1155 u32 bit07:1; 1156 u32 bit08:1; 1157 u32 bit09:1; 1158 u32 bit10:1; 1159 u32 bit11:1; 1160 u32 bit12:1; 1161 u32 bit13:1; 1162 u32 bit14:1; 1163 u32 bit15:1; 1164 u32 bit16:1; 1165 u32 bit17:1; 1166 u32 bit18:1; 1167 u32 bit19:1; 1168 u32 bit20:1; 1169 u32 bit21:1; 1170 u32 bit22:1; 1171 u32 bit23:1; 1172 u32 bit24:1; 1173 u32 bit25:1; 1174 u32 bit26:1; 1175 u32 bit27:1; 1176 u32 bit28:1; 1177 u32 bit29:1; 1178 u32 bit30:1; 1179 u32 bit31:1; 1180 } bits; 1181 }; 1182 #endif 1183