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Searched refs:ui32Base (Results 1 – 25 of 122) sorted by relevance

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/bsp/msp432e401y-LaunchPad/libraries/msp432e4/driverlib/
A Di2c.c91 _I2CBaseValid(uint32_t ui32Base) in _I2CBaseValid() argument
93 return ((ui32Base == I2C0_BASE) || (ui32Base == I2C1_BASE) || in _I2CBaseValid()
94 (ui32Base == I2C2_BASE) || (ui32Base == I2C3_BASE) || in _I2CBaseValid()
95 (ui32Base == I2C4_BASE) || (ui32Base == I2C5_BASE) || in _I2CBaseValid()
96 (ui32Base == I2C6_BASE) || (ui32Base == I2C7_BASE) || in _I2CBaseValid()
97 (ui32Base == I2C8_BASE) || (ui32Base == I2C9_BASE)); in _I2CBaseValid()
115 _I2CIntNumberGet(uint32_t ui32Base) in _I2CIntNumberGet() argument
195 I2CMasterEnable(ui32Base); in I2CMasterInitExpClk()
259 I2CSlaveEnable(ui32Base); in I2CSlaveInit()
354 I2CSlaveEnable(uint32_t ui32Base) in I2CSlaveEnable() argument
[all …]
A Duart.c99 return ((ui32Base == UART0_BASE) || (ui32Base == UART1_BASE) || in _UARTBaseValid()
100 (ui32Base == UART2_BASE) || (ui32Base == UART3_BASE) || in _UARTBaseValid()
101 (ui32Base == UART4_BASE) || (ui32Base == UART5_BASE) || in _UARTBaseValid()
102 (ui32Base == UART6_BASE) || (ui32Base == UART7_BASE)); in _UARTBaseValid()
188 HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & in UARTParityModeSet()
363 UARTDisable(ui32Base); in UARTConfigSetExpClk()
414 UARTEnable(ui32Base); in UARTConfigSetExpClk()
496 UARTEnable(uint32_t ui32Base) in UARTEnable() argument
902 HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) & in UARTFlowControlSet()
968 HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) & in UARTTxIntModeSet()
[all …]
A Dwatchdog.c72 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogRunning()
99 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogEnable()
127 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogResetEnable()
155 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogResetDisable()
180 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogLock()
206 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogUnlock()
232 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogLockState()
264 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogReloadSet()
290 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogReloadGet()
315 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogValueGet()
[all …]
A Dadc.c140 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntRegister()
185 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntUnregister()
223 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntDisable()
252 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntEnable()
290 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntStatus()
352 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntClear()
380 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCSequenceEnable()
408 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCSequenceDisable()
478 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCSequenceConfigure()
572 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCSequenceStepConfigure()
[all …]
A Dqei.c70 QEIEnable(uint32_t ui32Base) in QEIEnable() argument
75 ASSERT(ui32Base == QEI0_BASE); in QEIEnable()
95 QEIDisable(uint32_t ui32Base) in QEIDisable() argument
100 ASSERT(ui32Base == QEI0_BASE); in QEIDisable()
146 ASSERT(ui32Base == QEI0_BASE); in QEIConfigure()
151 HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & in QEIConfigure()
178 QEIPositionGet(uint32_t ui32Base) in QEIPositionGet() argument
261 QEIErrorGet(uint32_t ui32Base) in QEIErrorGet() argument
360 HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & in QEIFilterConfigure()
454 HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & in QEIVelocityConfigure()
[all …]
A Demac.c402 HWREG(ui32Base + EMAC_O_MIIADDR) = ((HWREG(ui32Base + EMAC_O_MIIADDR) & in EMACInit()
430 EMACReset(uint32_t ui32Base) in EMACReset() argument
1272 EMACNumAddrGet(uint32_t ui32Base) in EMACNumAddrGet() argument
1805 EMACStatusGet(uint32_t ui32Base) in EMACStatusGet() argument
2203 EMACTxFlush(uint32_t ui32Base) in EMACTxFlush() argument
2238 EMACTxEnable(uint32_t ui32Base) in EMACTxEnable() argument
2264 EMACTxDisable(uint32_t ui32Base) in EMACTxDisable() argument
2291 EMACRxEnable(uint32_t ui32Base) in EMACRxEnable() argument
2317 EMACRxDisable(uint32_t ui32Base) in EMACRxDisable() argument
4705 EMACWoLEnter(uint32_t ui32Base) in EMACWoLEnter() argument
[all …]
A Daes.c69 AESReset(uint32_t ui32Base) in AESReset() argument
74 ASSERT(ui32Base == AES_BASE); in AESReset()
185 ASSERT(ui32Base == AES_BASE); in AESConfigSet()
271 ASSERT(ui32Base == AES_BASE); in AESKey1Set()
327 ASSERT(ui32Base == AES_BASE); in AESKey2Set()
380 ASSERT(ui32Base == AES_BASE); in AESKey3Set()
410 ASSERT(ui32Base == AES_BASE); in AESIVSet()
441 ASSERT(ui32Base == AES_BASE); in AESIVRead()
479 ASSERT(ui32Base == AES_BASE); in AESTagRead()
526 ASSERT(ui32Base == AES_BASE); in AESLengthSet()
[all …]
A Dusb.c106 ASSERT(ui32Base == USB0_BASE); in _USBIndexWrite()
171 ASSERT(ui32Base == USB0_BASE); in _USBIndexRead()
230 USBHostSuspend(uint32_t ui32Base) in USBHostSuspend() argument
235 ASSERT(ui32Base == USB0_BASE); in USBHostSuspend()
267 ASSERT(ui32Base == USB0_BASE); in USBHostReset()
319 ASSERT(ui32Base == USB0_BASE); in USBHighSpeed()
470 USBDevSpeedGet(uint32_t ui32Base) in USBDevSpeedGet() argument
3878 USBModeGet(uint32_t ui32Base) in USBModeGet() argument
3916 USBHostMode(uint32_t ui32Base) in USBHostMode() argument
3941 USBDevMode(uint32_t ui32Base) in USBDevMode() argument
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A Dtimer.c89 _TimerBaseValid(uint32_t ui32Base) in _TimerBaseValid() argument
91 return ((ui32Base == TIMER0_BASE) || (ui32Base == TIMER1_BASE) || in _TimerBaseValid()
92 (ui32Base == TIMER2_BASE) || (ui32Base == TIMER3_BASE) || in _TimerBaseValid()
93 (ui32Base == TIMER4_BASE) || (ui32Base == TIMER5_BASE) || in _TimerBaseValid()
94 (ui32Base == TIMER6_BASE) || (ui32Base == TIMER7_BASE)); in _TimerBaseValid()
177 ASSERT(_TimerBaseValid(ui32Base)); in TimerEnable()
207 ASSERT(_TimerBaseValid(ui32Base)); in TimerDisable()
489 HWREG(ui32Base + TIMER_O_CTL) = ((HWREG(ui32Base + TIMER_O_CTL) & in TimerControlEvent()
606 TimerRTCEnable(uint32_t ui32Base) in TimerRTCEnable() argument
631 TimerRTCDisable(uint32_t ui32Base) in TimerRTCDisable() argument
[all …]
/bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/src/
A Di2c.c107 _I2CBaseValid(uint32_t ui32Base) in _I2CBaseValid() argument
109 return((ui32Base == I2C0_BASE) || (ui32Base == I2C1_BASE) || in _I2CBaseValid()
110 (ui32Base == I2C2_BASE) || (ui32Base == I2C3_BASE) || in _I2CBaseValid()
111 (ui32Base == I2C4_BASE) || (ui32Base == I2C5_BASE) || in _I2CBaseValid()
112 (ui32Base == I2C6_BASE) || (ui32Base == I2C7_BASE) || in _I2CBaseValid()
113 (ui32Base == I2C8_BASE) || (ui32Base == I2C9_BASE)); in _I2CBaseValid()
131 _I2CIntNumberGet(uint32_t ui32Base) in _I2CIntNumberGet() argument
218 I2CMasterEnable(ui32Base); in I2CMasterInitExpClk()
282 I2CSlaveEnable(ui32Base); in I2CSlaveInit()
380 I2CSlaveEnable(uint32_t ui32Base) in I2CSlaveEnable() argument
[all …]
A Dqei.c78 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIEnable()
103 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIDisable()
149 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIConfigure()
154 HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & in QEIConfigure()
186 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIPositionGet()
213 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIPositionSet()
242 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIDirectionGet()
269 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIErrorGet()
298 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIFilterEnable()
324 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIFilterDisable()
[all …]
A Duart.c116 return((ui32Base == UART0_BASE) || (ui32Base == UART1_BASE) || in _UARTBaseValid()
117 (ui32Base == UART2_BASE) || (ui32Base == UART3_BASE) || in _UARTBaseValid()
118 (ui32Base == UART4_BASE) || (ui32Base == UART5_BASE) || in _UARTBaseValid()
119 (ui32Base == UART6_BASE) || (ui32Base == UART7_BASE)); in _UARTBaseValid()
211 HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & in UARTParityModeSet()
388 UARTDisable(ui32Base); in UARTConfigSetExpClk()
439 UARTEnable(ui32Base); in UARTConfigSetExpClk()
523 UARTEnable(uint32_t ui32Base) in UARTEnable() argument
965 HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) & in UARTFlowControlSet()
1039 HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) & in UARTTxIntModeSet()
[all …]
A Dwatchdog.c75 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogRunning()
102 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogEnable()
130 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogResetEnable()
158 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogResetDisable()
183 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogLock()
209 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogUnlock()
235 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogLockState()
267 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogReloadSet()
293 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogReloadGet()
318 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogValueGet()
[all …]
A Dadc.c156 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntRegister()
201 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntUnregister()
239 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntDisable()
268 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntEnable()
306 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntStatus()
368 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntClear()
396 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCSequenceEnable()
424 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCSequenceDisable()
510 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCSequenceConfigure()
622 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCSequenceStepConfigure()
[all …]
A Demac.c406 HWREG(ui32Base + EMAC_O_MIIADDR) = ((HWREG(ui32Base + EMAC_O_MIIADDR) & in EMACInit()
434 EMACReset(uint32_t ui32Base) in EMACReset() argument
1276 EMACNumAddrGet(uint32_t ui32Base) in EMACNumAddrGet() argument
1809 EMACStatusGet(uint32_t ui32Base) in EMACStatusGet() argument
2207 EMACTxFlush(uint32_t ui32Base) in EMACTxFlush() argument
2242 EMACTxEnable(uint32_t ui32Base) in EMACTxEnable() argument
2268 EMACTxDisable(uint32_t ui32Base) in EMACTxDisable() argument
2295 EMACRxEnable(uint32_t ui32Base) in EMACRxEnable() argument
2321 EMACRxDisable(uint32_t ui32Base) in EMACRxDisable() argument
4709 EMACWoLEnter(uint32_t ui32Base) in EMACWoLEnter() argument
[all …]
A Daes.c72 AESReset(uint32_t ui32Base) in AESReset() argument
77 ASSERT(ui32Base == AES_BASE); in AESReset()
188 ASSERT(ui32Base == AES_BASE); in AESConfigSet()
274 ASSERT(ui32Base == AES_BASE); in AESKey1Set()
330 ASSERT(ui32Base == AES_BASE); in AESKey2Set()
383 ASSERT(ui32Base == AES_BASE); in AESKey3Set()
413 ASSERT(ui32Base == AES_BASE); in AESIVSet()
444 ASSERT(ui32Base == AES_BASE); in AESIVRead()
482 ASSERT(ui32Base == AES_BASE); in AESTagRead()
529 ASSERT(ui32Base == AES_BASE); in AESLengthSet()
[all …]
A Dtiva_timer.c119 _TimerBaseValid(uint32_t ui32Base) in _TimerBaseValid() argument
121 return((ui32Base == TIMER0_BASE) || (ui32Base == TIMER1_BASE) || in _TimerBaseValid()
122 (ui32Base == TIMER2_BASE) || (ui32Base == TIMER3_BASE) || in _TimerBaseValid()
123 (ui32Base == TIMER4_BASE) || (ui32Base == TIMER5_BASE) || in _TimerBaseValid()
124 (ui32Base == TIMER6_BASE) || (ui32Base == TIMER7_BASE) || in _TimerBaseValid()
125 (ui32Base == WTIMER0_BASE) || (ui32Base == WTIMER1_BASE) || in _TimerBaseValid()
126 (ui32Base == WTIMER2_BASE) || (ui32Base == WTIMER3_BASE) || in _TimerBaseValid()
127 (ui32Base == WTIMER4_BASE) || (ui32Base == WTIMER5_BASE)); in _TimerBaseValid()
546 HWREG(ui32Base + TIMER_O_CTL) = ((HWREG(ui32Base + TIMER_O_CTL) & in TimerControlEvent()
664 TimerRTCEnable(uint32_t ui32Base) in TimerRTCEnable() argument
[all …]
/bsp/tm4c129x/libraries/driverlib/
A Di2c.c107 _I2CBaseValid(uint32_t ui32Base) in _I2CBaseValid() argument
109 return((ui32Base == I2C0_BASE) || (ui32Base == I2C1_BASE) || in _I2CBaseValid()
110 (ui32Base == I2C2_BASE) || (ui32Base == I2C3_BASE) || in _I2CBaseValid()
111 (ui32Base == I2C4_BASE) || (ui32Base == I2C5_BASE) || in _I2CBaseValid()
112 (ui32Base == I2C6_BASE) || (ui32Base == I2C7_BASE) || in _I2CBaseValid()
113 (ui32Base == I2C8_BASE) || (ui32Base == I2C9_BASE)); in _I2CBaseValid()
131 _I2CIntNumberGet(uint32_t ui32Base) in _I2CIntNumberGet() argument
218 I2CMasterEnable(ui32Base); in I2CMasterInitExpClk()
282 I2CSlaveEnable(ui32Base); in I2CSlaveInit()
380 I2CSlaveEnable(uint32_t ui32Base) in I2CSlaveEnable() argument
[all …]
A Duart.c116 return((ui32Base == UART0_BASE) || (ui32Base == UART1_BASE) || in _UARTBaseValid()
117 (ui32Base == UART2_BASE) || (ui32Base == UART3_BASE) || in _UARTBaseValid()
118 (ui32Base == UART4_BASE) || (ui32Base == UART5_BASE) || in _UARTBaseValid()
119 (ui32Base == UART6_BASE) || (ui32Base == UART7_BASE)); in _UARTBaseValid()
211 HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & in UARTParityModeSet()
388 UARTDisable(ui32Base); in UARTConfigSetExpClk()
439 UARTEnable(ui32Base); in UARTConfigSetExpClk()
523 UARTEnable(uint32_t ui32Base) in UARTEnable() argument
1005 HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) & in UARTFlowControlSet()
1079 HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) & in UARTTxIntModeSet()
[all …]
A Dqei.c78 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIEnable()
103 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIDisable()
149 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIConfigure()
154 HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & in QEIConfigure()
186 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIPositionGet()
213 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIPositionSet()
242 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIDirectionGet()
269 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIErrorGet()
298 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIFilterEnable()
324 ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); in QEIFilterDisable()
[all …]
A Dwatchdog.c75 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogRunning()
102 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogEnable()
130 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogResetEnable()
158 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogResetDisable()
183 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogLock()
209 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogUnlock()
235 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogLockState()
267 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogReloadSet()
293 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogReloadGet()
318 ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE)); in WatchdogValueGet()
[all …]
A Dadc.c156 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntRegister()
201 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntUnregister()
239 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntDisable()
268 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntEnable()
306 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntStatus()
368 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCIntClear()
396 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCSequenceEnable()
424 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCSequenceDisable()
510 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCSequenceConfigure()
627 ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); in ADCSequenceStepConfigure()
[all …]
A Demac.c406 HWREG(ui32Base + EMAC_O_MIIADDR) = ((HWREG(ui32Base + EMAC_O_MIIADDR) & in EMACInit()
434 EMACReset(uint32_t ui32Base) in EMACReset() argument
1276 EMACNumAddrGet(uint32_t ui32Base) in EMACNumAddrGet() argument
1809 EMACStatusGet(uint32_t ui32Base) in EMACStatusGet() argument
2207 EMACTxFlush(uint32_t ui32Base) in EMACTxFlush() argument
2242 EMACTxEnable(uint32_t ui32Base) in EMACTxEnable() argument
2268 EMACTxDisable(uint32_t ui32Base) in EMACTxDisable() argument
2295 EMACRxEnable(uint32_t ui32Base) in EMACRxEnable() argument
2321 EMACRxDisable(uint32_t ui32Base) in EMACRxDisable() argument
4709 EMACWoLEnter(uint32_t ui32Base) in EMACWoLEnter() argument
[all …]
A Daes.c72 AESReset(uint32_t ui32Base) in AESReset() argument
77 ASSERT(ui32Base == AES_BASE); in AESReset()
188 ASSERT(ui32Base == AES_BASE); in AESConfigSet()
274 ASSERT(ui32Base == AES_BASE); in AESKey1Set()
330 ASSERT(ui32Base == AES_BASE); in AESKey2Set()
383 ASSERT(ui32Base == AES_BASE); in AESKey3Set()
413 ASSERT(ui32Base == AES_BASE); in AESIVSet()
444 ASSERT(ui32Base == AES_BASE); in AESIVRead()
482 ASSERT(ui32Base == AES_BASE); in AESTagRead()
529 ASSERT(ui32Base == AES_BASE); in AESLengthSet()
[all …]
A Dtiva_timer.c119 _TimerBaseValid(uint32_t ui32Base) in _TimerBaseValid() argument
121 return((ui32Base == TIMER0_BASE) || (ui32Base == TIMER1_BASE) || in _TimerBaseValid()
122 (ui32Base == TIMER2_BASE) || (ui32Base == TIMER3_BASE) || in _TimerBaseValid()
123 (ui32Base == TIMER4_BASE) || (ui32Base == TIMER5_BASE) || in _TimerBaseValid()
124 (ui32Base == TIMER6_BASE) || (ui32Base == TIMER7_BASE) || in _TimerBaseValid()
125 (ui32Base == WTIMER0_BASE) || (ui32Base == WTIMER1_BASE) || in _TimerBaseValid()
126 (ui32Base == WTIMER2_BASE) || (ui32Base == WTIMER3_BASE) || in _TimerBaseValid()
127 (ui32Base == WTIMER4_BASE) || (ui32Base == WTIMER5_BASE)); in _TimerBaseValid()
549 HWREG(ui32Base + TIMER_O_CTL) = ((HWREG(ui32Base + TIMER_O_CTL) & in TimerControlEvent()
667 TimerRTCEnable(uint32_t ui32Base) in TimerRTCEnable() argument
[all …]

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