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Searched refs:uint32 (Results 1 – 25 of 89) sorted by relevance

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/bsp/rm48x50/HALCoGen/include/
A Dstd_nhet.h26 uint32 program_word ;
27 uint32 control_word ;
28 uint32 data_word ;
29 uint32 reserved_word ;
38 uint32 : 6 ;
39 uint32 reqnum : 3 ;
40 uint32 brk : 1 ;
1240 uint32 program_word ;
1241 uint32 control_word ;
1242 uint32 data_word ;
[all …]
A Dreg_dma.h37 uint32 GCTRL; /**< 0x0000: Global Control Register */
38 uint32 PEND; /**< 0x0004: Channel Pending Register */
39 uint32 FBREG; /**< 0x0008: Fall Back Register */
40 uint32 DMASTAT; /**< 0x000C: Status Register */
41 uint32 rsvd1; /**< 0x0010: Reserved */
42 uint32 HWCHENAS; /**< 0x0014: HW Channel Enable Set */
43 uint32 rsvd2; /**< 0x0018: Reserved */
44 uint32 HWCHENAR; /**< 0x001C: HW Channel Enable Reset */
116 uint32 PAACSADDR; /**< 0x018C: */
117 uint32 PAACDADDR; /**< 0x0190: */
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A Dreg_system.h133 uint32 PLLCTL3; /* 0x0000 */
134 uint32 rsvd1; /* 0x0004 */
135 uint32 STCCLKDIV; /* 0x0008 */
137 uint32 ECPCNTRL0; /* 0x0024 */
140 uint32 VCLKACON1; /* 0x0040 */
142 uint32 CLKSLIP; /* 0x0070 */
144 uint32 EFC_CTLEN; /* 0x00EC */
145 uint32 DIEIDL_REG0; /* 0x00F0 */
146 uint32 DIEIDH_REG1; /* 0x00F4 */
147 uint32 DIEIDL_REG2; /* 0x00F8 */
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A Dreg_adc.h39 uint32 RSTCR; /**< 0x0000: Reset control register */
40 uint32 OPMODECR; /**< 0x0004: Operating mode control register */
41 uint32 CLOCKCR; /**< 0x0008: Clock control register */
42 uint32 CALCR; /**< 0x000C: Calibration control register */
43 uint32 GxMODECR[3U]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */
44 uint32 G0SRC; /**< 0x001C: Group 0 trigger source control register */
45 uint32 G1SRC; /**< 0x0020: Group 1 trigger source control register */
135 #define adcRAM1 (*(volatile uint32 *)0xFF3E0000U)
142 #define adcRAM2 (*(volatile uint32 *)0xFF3A0000U)
149 #define adcPARRAM1 (*(volatile uint32 *)(0xFF3E0000U + 0x1000U))
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A Dreg_flash.h33 uint32 FRDCNTL; /* 0x0000 */
34 uint32 FSPRD; /* 0x0004 */
35 uint32 FEDACCTRL1; /* 0x0008 */
36 uint32 FEDACCTRL2; /* 0x000C */
37 uint32 FCORERRCNT; /* 0x0010 */
38 uint32 FCORERRADD; /* 0x0014 */
39 uint32 FCORERRPOS; /* 0x0018 */
40 uint32 FEDACSTATUS; /* 0x001C */
41 uint32 FUNCERRADD; /* 0x0020 */
42 uint32 FEDACSDIS; /* 0x0024 */
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A Dreg_het.h41 uint32 GCR; /**< 0x0000: Global control register */
42 uint32 PFR; /**< 0x0004: Prescale factor register */
43 uint32 ADDR; /**< 0x0008: Current address register */
44 uint32 OFF1; /**< 0x000C: Interrupt offset register 1 */
45 uint32 OFF2; /**< 0x0010: Interrupt offset register 2 */
46 uint32 INTENAS; /**< 0x0014: Interrupt enable set register */
52 uint32 AND; /**< 0x002C: AND share control register */
142 #define NHET1RAMPARLOC (*(volatile uint32 *)0xFF462000U)
143 #define NHET1RAMLOC (*(volatile uint32 *)0xFF460000U)
145 #define NHET2RAMPARLOC (*(volatile uint32 *)0xFF442000U)
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A Dreg_crc.h40 uint32 rsvd1; /**< 0x0004: reserved >**/
42 uint32 rsvd2; /**< 0x000C: reserved >**/
44 uint32 rsvd3; /**< 0x0014: reserved >**/
46 uint32 rsvd4; /**< 0x001C: reserved >**/
48 uint32 rsvd5; /**< 0x0024: reserved >**/
50 uint32 rsvd6; /**< 0x002C: reserved >**/
51 uint32 INT_OFFSET_REG; /**< 0x0030: Interrupt Offset >**/
52 uint32 rsvd7; /**< 0x0034: reserved >**/
54 uint32 rsvd8; /**< 0x003C: reserved >**/
60 uint32 rsvd9[3]; /**< 0x0054: reserved >**/
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A Demac.h89 uint32 ctrlCore, uint32 channel);
96 extern void EMACRMIISpeedSet(uint32 emacBase, uint32 speed);
97 extern void EMACDuplexSet(uint32 emacBase, uint32 duplexMode);
104 extern void EMACInit(uint32 emacCtrlBase, uint32 emacBase);
106 extern void EMACMACAddrSet(uint32 emacBase, uint32 channel,
109 extern void EMACRxUnicastSet(uint32 emacBase, uint32 channel);
110 extern void EMACCoreIntAck(uint32 emacBase, uint32 eoiFlag);
111 extern void EMACTxCPWrite(uint32 emacBase, uint32 channel,
113 extern void EMACRxCPWrite(uint32 emacBase, uint32 channel,
116 extern void EMACNumFreeBufSet(uint32 emacBase, uint32 channel,
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A Dreg_mibspi.h43 uint32 LVL; /**< 0x000C: Interrupt Level */
46 uint32 PCDIR; /**< 0x0018: Pin Direction */
49 uint32 PCSET; /**< 0x0024: Output Pin Set */
50 uint32 PCCLR; /**< 0x0028: Output Pin Clr */
54 uint32 DAT0; /**< 0x0038: Transmit Data */
58 uint32 DELAY; /**< 0x0048: Delays */
74 uint32 rsvd1[2U]; /**< 0x0088: Reserved */
81 uint32 rsvd2; /**< 0x011C: Reserved */
87 uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */
88 uint32 EXT_PRESCALE1; /**< 0x0138: */
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A Dreg_pinmux.h26 #define REVISION_REG (*(volatile uint32 *)0xFFFFEA00U)
27 #define ENDIAN_REG (*(volatile uint32 *)0xFFFFEA20U)
41 uint32 rsvd; /* Reserved */
54 uint32 KICKER0; /* kicker 0 register */
55 uint32 KICKER1; /* kicker 1 register */
70 uint32 PINMMR0; /**< 0xEB10 Pin Mux 0 register*/
71 uint32 PINMMR1; /**< 0xEB14 Pin Mux 1 register*/
72 uint32 PINMMR2; /**< 0xEB18 Pin Mux 2 register*/
73 uint32 PINMMR3; /**< 0xEB1C Pin Mux 3 register*/
74 uint32 PINMMR4; /**< 0xEB20 Pin Mux 4 register*/
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A Dreg_can.h39 uint32 CTL; /**< 0x0000: Control Register */
40 uint32 ES; /**< 0x0004: Error and Status Register */
41 uint32 EERC; /**< 0x0008: Error Counter Register */
42 uint32 BTR; /**< 0x000C: Bit Timing Register */
43 uint32 INT; /**< 0x0010: Interrupt Register */
134 #define canRAM1 (*(volatile uint32 *)0xFF1E0000U)
141 #define canRAM2 (*(volatile uint32 *)0xFF1C0000U)
148 #define canRAM3 (*(volatile uint32 *)0xFF1A0000U)
156 #define canPARRAM1 (*(volatile uint32 *)(0xFF1E0000U + 0x10U))
164 #define canPARRAM2 (*(volatile uint32 *)(0xFF1C0000U + 0x10U))
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A Dreg_htu.h39 uint32 GC; /** 0x00 */
45 uint32 ACPE; /** 0x18 */
63 uint32 ID; /** 0x60 */
74 uint32 IFADDRA;
75 uint32 IFADDRB;
76 uint32 IHADDRCT;
77 uint32 ITCOUNT;
82 uint32 CFADDRA;
83 uint32 CFADDRB;
84 uint32 CFCOUNT;
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A Dreg_dmm.h41 uint32 GLBCTRL; /**< 0x0000: Global control register 0 */
42 uint32 INTSET; /**< 0x0004: DMM Interrupt Set Register */
43 uint32 INTCLR; /**< 0x0008: DMM Interrupt Clear Register */
45 uint32 INTFLG; /**< 0x0010: DMM Interrupt Flag Register */
62 uint32 DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */
63 uint32 DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */
64 uint32 DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */
70 uint32 PC2; /**< 0x0074: DMM Pin Control 2 */
71 uint32 PC3; /**< 0x0078: DMM Pin Control 3 */
72 uint32 PC4; /**< 0x007C: DMM Pin Control 4 */
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A Dsystem.h211 uint32 CONFIG_SYSPC1;
212 uint32 CONFIG_SYSPC2;
213 uint32 CONFIG_SYSPC7;
214 uint32 CONFIG_SYSPC8;
215 uint32 CONFIG_SYSPC9;
216 uint32 CONFIG_CSDIS;
217 uint32 CONFIG_CDDIS;
392 uint32 CONFIG_FBSE;
393 uint32 CONFIG_FBAC;
395 uint32 CONFIG_FPAC1;
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A Dreg_vim.h36 uint32 IRQINDEX; /* 0x0000 */
37 uint32 FIQINDEX; /* 0x0004 */
38 uint32 rsvd1; /* 0x0008 */
39 uint32 rsvd2; /* 0x000C */
40 uint32 FIRQPR0; /* 0x0010 */
41 uint32 FIRQPR1; /* 0x0014 */
42 uint32 FIRQPR2; /* 0x0018 */
43 uint32 FIRQPR3; /* 0x001C */
44 uint32 INTREQ0; /* 0x0020 */
45 uint32 INTREQ1; /* 0x0024 */
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A Dreg_pom.h34 uint32 POMGLBCTRL_UL; /* 0x00 */
35 uint32 POMREV_UL; /* 0x04 */
36 uint32 POMCLKCTRL_UL; /* 0x08 */
37 uint32 POMFLG_UL; /* 0x0C */
40 uint32 rsdv1;
44 uint32 POMPROGSTART_UL;
45 uint32 POMOVLSTART_UL;
46 uint32 POMREGSIZE_UL;
47 uint32 rsdv2;
62 uint32 Reserved_Reg_UL;
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A Dreg_rti.h39 uint32 GCTRL; /**< 0x0000: Global Control Register */
40 uint32 TBCTRL; /**< 0x0004: Timebase Control Register */
41 uint32 CAPCTRL; /**< 0x0008: Capture Control Register */
42 uint32 COMPCTRL; /**< 0x000C: Compare Control Register */
73 uint32 WDSTATUS; /**< 0x0098: Watchdog Status Register */
74 uint32 WDKEY; /**< 0x009C: Watchdog Key Register */
75 uint32 DWDCNTR; /**< 0x00A0: Digital Watchdog Down Counter */
79 uint32 COMP0CLR; /**< 0x00B0: RTI Compare 0 Clear Register */
80 uint32 COMP1CLR; /**< 0x00B4: RTI Compare 1 Clear Register */
81 uint32 COMP2CLR; /**< 0x00B8: RTI Compare 2 Clear Register */
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A Dreg_pcr.h36 uint32 PMPROTSET0; /* 0x0000 */
37 uint32 PMPROTSET1; /* 0x0004 */
38 uint32 rsvd1[2U]; /* 0x0008 */
39 uint32 PMPROTCLR0; /* 0x0010 */
40 uint32 PMPROTCLR1; /* 0x0014 */
42 uint32 PPROTSET0; /* 0x0020 */
43 uint32 PPROTSET1; /* 0x0024 */
44 uint32 PPROTSET2; /* 0x0028 */
45 uint32 PPROTSET3; /* 0x002C */
47 uint32 PPROTCLR0; /* 0x0040 */
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A Dreg_lin.h41 uint32 GCR0; /**< 0x0000: Global control register 0 */
42 uint32 GCR1; /**< 0x0004: Global control register 1 */
43 uint32 GCR2; /**< 0x0008: Global control register 2 */
44 uint32 SETINT; /**< 0x000C: Set interrupt enable register */
45 uint32 CLRINT; /**< 0x0010: Clear interrupt enable register */
46 uint32 SETINTLVL; /**< 0x0014: Set interrupt level register */
47 uint32 CLRINTLVL; /**< 0x0018: Set interrupt level register */
48 uint32 FLR; /**< 0x001C: interrupt flag register */
49 uint32 INTVECT0; /**< 0x0020: interrupt vector Offset 0 */
50 uint32 INTVECT1; /**< 0x0024: interrupt vector Offset 1 */
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A Dreg_i2c.h41 uint32 OAR; /**< 0x0000 I2C Own Address register */
42 uint32 IMR; /**< 0x0004 I2C Interrupt Mask/Status register */
43 uint32 STR; /**< 0x0008 I2C Interrupt Status register */
44 uint32 CLKL; /**< 0x000C I2C Clock Divider Low register */
45 uint32 CLKH; /**< 0x0010 I2C Clock Divider High register */
46 uint32 CNT; /**< 0x0014 I2C Data Count register */
47 uint32 DRR; /**< 0x0018 I2C Data Receive register */
48 uint32 SAR; /**< 0x001C I2C Slave Address register */
49 uint32 DXR; /**< 0x0020 I2C Data Transmit register */
50 uint32 MDR; /**< 0x0024 I2C Mode register */
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A Dsys_dma.h185 uint32 ISADDR;
186 uint32 IDADDR;
189 uint32 CHCTRL;
190 uint32 EIOFF;
191 uint32 FIOFF;
202 uint32 CSADDR;
203 uint32 CDADDR;
204 uint32 CTCOUNT;
235 void dmaSetChEnable(uint32 channel,uint32 type);
236 void dmaReqAssign(uint32 channel,uint32 reqline);
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A Dreg_spi.h40 uint32 GCR0; /**< 0x0000: Global Control 0 */
43 uint32 LVL; /**< 0x000C: Interrupt Level */
46 uint32 PCDIR; /**< 0x0018: Pin Direction */
49 uint32 PCSET; /**< 0x0024: Output Pin Set */
50 uint32 PCCLR; /**< 0x0028: Output Pin Clr */
54 uint32 DAT0; /**< 0x0038: Transmit Data */
58 uint32 DELAY; /**< 0x0048: Delays */
60 uint32 FMT0; /**< 0x0050: Data Format 0 */
61 uint32 FMT1; /**< 0x0054: Data Format 1 */
62 uint32 FMT2; /**< 0x0058: Data Format 2 */
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A Dreg_sci.h47 uint32 FLR; /**< 0x001C Interrupt Flag Register */
50 uint32 FORMAT; /**< 0x0028 Format Control Register */
52 uint32 ED; /**< 0x0030 Emulation Register */
53 uint32 RD; /**< 0x0034 Receive Data Buffer */
54 uint32 TD; /**< 0x0038 Transmit Data Buffer */
55 uint32 FUN; /**< 0x003C Pin Function Register */
56 uint32 DIR; /**< 0x0040 Pin Direction Register */
57 uint32 DIN; /**< 0x0044 Pin Data In Register */
58 uint32 DOUT; /**< 0x0048 Pin Data Out Register */
59 uint32 SET; /**< 0x004C Pin Data Set Register */
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A Dsys_selftest.h124 uint32 CONFIG_RAMT;
125 uint32 CONFIG_DLR;
126 uint32 CONFIG_PACT;
128 uint32 CONFIG_OVER;
130 uint32 CONFIG_ROM;
131 uint32 CONFIG_ALGO;
161 void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 …
172 void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 …
191 uint32 CONFIG_STCGCR0;
305 uint32 CONFIG_PINS;
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A Dreg_esm.h39 uint32 EPENASET1; /* 0x0000 */
40 uint32 EPENACLR1; /* 0x0004 */
41 uint32 INTENASET1; /* 0x0008 */
42 uint32 INTENACLR1; /* 0x000C */
43 uint32 INTLVLSET1; /* 0x0010 */
44 uint32 INTLVLCLR1; /* 0x0014 */
45 uint32 ESTATUS1[3U]; /* 0x0018, 0x001C, 0x0020 */
46 uint32 EPSTATUS; /* 0x0024 */
47 uint32 INTOFFH; /* 0x0028 */
48 uint32 INTOFFL; /* 0x002C */
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