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/bsp/allwinner/libraries/sunxi-hal/hal/source/gmac/
A Dhal_geth_utils.c59 uint32_t value; in geth_set_link_mode() local
87 uint32_t value; in geth_mac_loopback() local
100 uint32_t value; in geth_start_tx() local
109 uint32_t value; in geth_stop_tx() local
118 uint32_t value; in geth_start_rx() local
127 uint32_t value; in geth_stop_rx() local
136 uint32_t value; in geth_loopback_enable() local
145 uint32_t value; in geth_loopback_disable() local
161 while(value) in geth_mac_reset()
193 value |= 0x1; in geth_set_filter()
[all …]
/bsp/CME_M7/StdPeriph_Driver/src/
A Dcmem7_efuse.c125 value = (value == 0) ? 1 : value; in EFUSE_Init()
130 value = (value == 0) ? 1 : value; in EFUSE_Init()
134 value = (value == 0) ? 1 : value; in EFUSE_Init()
138 value = (value == 0) ? 1 : value; in EFUSE_Init()
142 value = (value == 0) ? 1 : value; in EFUSE_Init()
146 value = (value == 0) ? 1 : value; in EFUSE_Init()
150 value = (value == 0) ? 1 : value; in EFUSE_Init()
154 value = (value == 0) ? 1 : value; in EFUSE_Init()
158 value = (value == 0) ? 1 : value; in EFUSE_Init()
162 value = (value == 0) ? 1 : value; in EFUSE_Init()
[all …]
/bsp/renesas/rzt2m_rsk/rzt/arm/CMSIS_5/CMSIS/Core_R/Include/
A Dcmsis_cp15.h102 __set_CP(15, 2, value, 0, 0, 0); in __set_CSSELR()
123 __set_CP(15, 0, value, 1, 0, 0); in __set_SCTLR()
142 __set_CP(15, 0, value, 1, 0, 1); in __set_ACTLR()
160 __set_CP(15, 0, value, 1, 0, 2); in __set_CPACR()
184 __set_CP(15, 0, value, 2, 0, 0); in __set_TTBR0()
208 __set_CP(15, 0, value, 3, 0, 0); in __set_DACR()
224 __set_CP(15, 0, value, 4, 6, 0); in __set_ICC_PMR()
242 __set_CP(15, 0, value, 5, 0, 0); in __set_DFSR()
260 __set_CP(15, 0, value, 5, 0, 1); in __set_IFSR()
743 __set_CP64(15, 0, value, 12); in __set_ICC_SGI1R()
[all …]
/bsp/renesas/rzn2l_etherkit/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/
A Dcmsis_cp15.h102 __set_CP(15, 2, value, 0, 0, 0); in __set_CSSELR()
123 __set_CP(15, 0, value, 1, 0, 0); in __set_SCTLR()
142 __set_CP(15, 0, value, 1, 0, 1); in __set_ACTLR()
160 __set_CP(15, 0, value, 1, 0, 2); in __set_CPACR()
184 __set_CP(15, 0, value, 2, 0, 0); in __set_TTBR0()
208 __set_CP(15, 0, value, 3, 0, 0); in __set_DACR()
224 __set_CP(15, 0, value, 4, 6, 0); in __set_ICC_PMR()
242 __set_CP(15, 0, value, 5, 0, 0); in __set_DFSR()
260 __set_CP(15, 0, value, 5, 0, 1); in __set_IFSR()
743 __set_CP64(15, 0, value, 12); in __set_ICC_SGI1R()
[all …]
/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/
A Dcmsis_cp15.h102 __set_CP(15, 2, value, 0, 0, 0); in __set_CSSELR()
123 __set_CP(15, 0, value, 1, 0, 0); in __set_SCTLR()
142 __set_CP(15, 0, value, 1, 0, 1); in __set_ACTLR()
160 __set_CP(15, 0, value, 1, 0, 2); in __set_CPACR()
184 __set_CP(15, 0, value, 2, 0, 0); in __set_TTBR0()
208 __set_CP(15, 0, value, 3, 0, 0); in __set_DACR()
224 __set_CP(15, 0, value, 4, 6, 0); in __set_ICC_PMR()
242 __set_CP(15, 0, value, 5, 0, 0); in __set_DFSR()
260 __set_CP(15, 0, value, 5, 0, 1); in __set_IFSR()
743 __set_CP64(15, 0, value, 12); in __set_ICC_SGI1R()
[all …]
/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/
A Dhal_fll.h151 #define FLL_CONF1_MODE_GET(value) ((((unsigned int)(value)) >> 16) & 0x1) argument
171 #define FLL_CONF2_GAIN_GET(value) ((((unsigned int)(value)) >> 0) & 0xF) argument
173 #define FLL_CONF2_GAIN(value) ((value) << 0) argument
177 #define FLL_CONF2_ASSERT_CYCLES(value) ((value) << 4) argument
181 #define FLL_CONF2_DEASSERT_CYCLES(value) ((value) << 10) argument
185 #define FLL_CONF2_TOLERANCE(value) ((value) << 16) argument
189 #define FLL_CONF2_STA_CLOCK(value) ((value) << 29) argument
193 #define FLL_CONF2_OPEN_LOOP(value) ((value) << 30) argument
197 #define FLL_CONF2_DITHER(value) ((value) << 31) argument
201 #define FLL_INTEGRATOR_FRACT(value) ((value) << 6) argument
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/prcm/prcm-sun50iw11/
A Dpower.c48 volatile u32 value; in ccu_set_poweroff_gating_state() local
108 u32 value = 0; in ccu_24mhosc_disable() local
118 value = readl(XO_CTRL_REG); in ccu_24mhosc_disable()
120 writel(value, XO_CTRL_REG); in ccu_24mhosc_disable()
130 writel(value, CCU_PLL_CTRL1); in ccu_24mhosc_disable()
132 value &= (~(0x1 << 0)); in ccu_24mhosc_disable()
140 u32 value = 0; in ccu_24mhosc_enable() local
147 value |= (0x1 << 0); in ccu_24mhosc_enable()
157 value &= (~(0x7 << 16)); in ccu_24mhosc_enable()
166 value = readl(XO_CTRL_REG); in ccu_24mhosc_enable()
[all …]
/bsp/allwinner_tina/libcpu/
A Dmmu.c24 value = 0; in mmu_setttbase()
43 orr value, value, #0x01 in mmu_enable()
55 bic value, value, #0x01 in mmu_disable()
67 orr value, value, #0x1000 in mmu_enable_icache()
79 orr value, value, #0x04 in mmu_enable_dcache()
91 bic value, value, #0x1000 in mmu_disable_icache()
103 bic value, value, #0x04 in mmu_disable_dcache()
115 orr value, value, #0x02 in mmu_enable_alignfault()
127 bic value, value, #0x02 in mmu_disable_alignfault()
180 value = 0; in mmu_invalidate_tlb()
[all …]
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/
A Dnvmctrl.h73 #define NVMCTRL_CTRLA_CMD(value) (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)) argument
106 #define NVMCTRL_CTRLA_CMDEX(value) (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)) argument
134 #define NVMCTRL_CTRLB_RWS(value) (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)) argument
186 #define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)) argument
321 #define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)) argument
338 #define NVMCTRL_LOCK_LOCK(value) (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)) argument
452 #define FUSES_OSC32K_CAL(value) (FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos)) argument
582 #define USB_FUSES_TRANSN(value) (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos)) argument
587 #define USB_FUSES_TRANSP(value) (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos)) argument
592 #define USB_FUSES_TRIM(value) (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos)) argument
[all …]
/bsp/microchip/same54/bsp/include/component/
A Dpicop.h71 #define PICOP_ID_ID(value) (PICOP_ID_ID_Msk & ((value) << PICOP_ID_ID_Pos)) argument
94 #define PICOP_CONFIG_ISA(value) (PICOP_CONFIG_ISA_Msk & ((value) << PICOP_CONFIG_ISA_Pos)) argument
417 #define PICOP_PC_PC(value) (PICOP_PC_PC_Msk & ((value) << PICOP_PC_PC_Pos)) argument
435 #define PICOP_HF_HF(value) (PICOP_HF_HF_Msk & ((value) << PICOP_HF_HF_Pos)) argument
754 #define PICOP_R3R0_R0(value) (PICOP_R3R0_R0_Msk & ((value) << PICOP_R3R0_R0_Pos)) argument
757 #define PICOP_R3R0_R1(value) (PICOP_R3R0_R1_Msk & ((value) << PICOP_R3R0_R1_Pos)) argument
760 #define PICOP_R3R0_R2(value) (PICOP_R3R0_R2_Msk & ((value) << PICOP_R3R0_R2_Pos)) argument
1112 #define PICOP_SP_R0(value) (PICOP_SP_R0_Msk & ((value) << PICOP_SP_R0_Pos)) argument
1115 #define PICOP_SP_R1(value) (PICOP_SP_R1_Msk & ((value) << PICOP_SP_R1_Pos)) argument
1118 #define PICOP_SP_R2(value) (PICOP_SP_R2_Msk & ((value) << PICOP_SP_R2_Pos)) argument
[all …]
A Dicm.h76 #define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)) argument
85 #define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)) argument
184 #define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)) argument
187 #define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)) argument
190 #define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)) argument
193 #define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)) argument
196 #define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)) argument
199 #define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)) argument
226 #define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)) argument
229 #define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)) argument
[all …]
/bsp/allwinner/libraries/drivers/
A Dlcd_cfg.c21 .v.value = 1,
46 .v.value = 272,
51 .v.value = 80,
56 .v.value = 47,
61 .v.value = 10,
88 .v.value = 5,
93 .v.value = 6,
98 .v.value = 1,
103 .v.value = 0,
108 .v.value = 0,
[all …]
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/
A Dnvmctrl.h76 #define NVMCTRL_CTRLA_CMD(value) ((NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))) argument
105 #define NVMCTRL_CTRLA_CMDEX(value) ((NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos… argument
133 #define NVMCTRL_CTRLB_RWS(value) ((NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))) argument
181 #define NVMCTRL_PARAM_NVMP(value) ((NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))) argument
184 #define NVMCTRL_PARAM_PSZ(value) ((NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))) argument
316 #define NVMCTRL_ADDR_ADDR(value) ((NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))) argument
334 #define NVMCTRL_LOCK_LOCK(value) ((NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))) argument
376 #define ADC_FUSES_BIASCAL(value) ((ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))) argument
419 #define FUSES_OSC32KCAL(value) ((FUSES_OSC32KCAL_Msk & ((value) << FUSES_OSC32KCAL_Pos))) argument
464 #define NVMCTRL_FUSES_PSZ(value) ((NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos))) argument
[all …]
/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/soc/
A Dv459_perf1.c30 .v.value = 1,
40 .v.value = 150,
45 .v.value = 4,
60 .v.value = 36,
65 .v.value = 65,
70 .v.value = 25,
75 .v.value = 1,
80 .v.value = 9,
90 .v.value = 1,
110 .v.value = 8,
[all …]
A Drgb_config.c30 .v.value = 1,
60 .v.value = 80,
65 .v.value = 47,
70 .v.value = 10,
97 .v.value = 5,
102 .v.value = 6,
107 .v.value = 1,
112 .v.value = 0,
117 .v.value = 0,
122 .v.value = 0,
[all …]
A Dtft08006_mipi_config.c30 .v.value = 1,
40 .v.value = 50,
45 .v.value = 4,
60 .v.value = 52,
65 .v.value = 52,
70 .v.value = 68,
75 .v.value = 1,
80 .v.value = 2,
90 .v.value = 1,
125 .v.value = 4,
[all …]
/bsp/microchip/saml10/bsp/include/component/
A Dnvmctrl.h62 #define NVMCTRL_CTRLA_CMD(value) (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_… argument
81 #define NVMCTRL_CTRLA_CMDEX(value) (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CM… argument
113 #define NVMCTRL_CTRLB_RWS(value) (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_… argument
718 #define ADC_FUSES_BIASCOMP(value) (ADC_FUSES_BIASCOMP_Msk & ((value) << ADC_FUSES_BIASCOMP_Pos)) argument
723 #define ADC_FUSES_BIASREFBUF(value) (ADC_FUSES_BIASREFBUF_Msk & ((value) << ADC_FUSES_BIASREFBUF_Po… argument
733 #define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos)) argument
964 #define FUSES_HOT_INT1V_VAL(value) (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos)) argument
1012 #define NVMCTRL_FUSES_SULCK(value) (NVMCTRL_FUSES_SULCK_Msk & ((value) << NVMCTRL_FUSES_SULCK_Pos)) argument
1029 #define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)) argument
1034 #define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)) argument
[all …]
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_trng.c126 #define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value)) argument
186 #define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value)) argument
249 #define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value)) argument
316 #define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value)) argument
383 #define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value)) argument
450 #define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value)) argument
517 #define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value)) argument
582 #define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value)) argument
777 #define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value)) argument
958 #define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value)) argument
[all …]
/bsp/microchip/same70/bsp/same70b/include/component/
A Dicm.h83 #define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)) argument
203 #define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)) argument
206 #define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)) argument
209 #define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)) argument
212 #define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)) argument
215 #define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)) argument
218 #define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)) argument
249 #define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)) argument
252 #define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)) argument
255 #define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)) argument
[all …]
/bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/
A Dcore_riscv.c55 void __set_FFLAGS(uint32_t value) in __set_FFLAGS() argument
84 void __set_FRM(uint32_t value) in __set_FRM() argument
113 void __set_FCSR(uint32_t value) in __set_FCSR() argument
142 void __set_MSTATUS(uint32_t value) in __set_MSTATUS() argument
171 void __set_MISA(uint32_t value) in __set_MISA() argument
200 void __set_MIE(uint32_t value) in __set_MIE() argument
229 void __set_MTVEC(uint32_t value) in __set_MTVEC() argument
285 void __set_MEPC(uint32_t value) in __set_MEPC() argument
312 void __set_MCAUSE(uint32_t value) in __set_MCAUSE() argument
339 void __set_MTVAL(uint32_t value) in __set_MTVAL() argument
[all …]
/bsp/fm33lc026/libraries/FM/FM33xx/Include/
A Dcore_cmInstr.h180 #define __BKPT(value) __breakpoint(value) argument
199 for (value >>= 1; value; value >>= 1) in __RBIT()
202 result |= value & 1; in __RBIT()
262 #define __STREXB(value, ptr) __strex(value, ptr) argument
274 #define __STREXH(value, ptr) __strex(value, ptr) argument
286 #define __STREXW(value, ptr) __strex(value, ptr) argument
373 #define __STRBT(value, ptr) __strt(value, ptr) argument
383 #define __STRHT(value, ptr) __strt(value, ptr) argument
393 #define __STRT(value, ptr) __strt(value, ptr) argument
566 #define __BKPT(value) __ASM volatile ("bkpt "#value) argument
[all …]
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/
A Dcore_cmInstr.h180 #define __BKPT(value) __breakpoint(value) argument
199 for (value >>= 1; value; value >>= 1) in __RBIT()
202 result |= value & 1; in __RBIT()
262 #define __STREXB(value, ptr) __strex(value, ptr) argument
274 #define __STREXH(value, ptr) __strex(value, ptr) argument
286 #define __STREXW(value, ptr) __strex(value, ptr) argument
373 #define __STRBT(value, ptr) __strt(value, ptr) argument
383 #define __STRHT(value, ptr) __strt(value, ptr) argument
393 #define __STRT(value, ptr) __strt(value, ptr) argument
566 #define __BKPT(value) __ASM volatile ("bkpt "#value) argument
[all …]
/bsp/apm32/libraries/APM32F4xx_Library/CMSIS/Include/
A Dcore_cmInstr.h180 #define __BKPT(value) __breakpoint(value) argument
199 for (value >>= 1; value; value >>= 1) in __RBIT()
202 result |= value & 1; in __RBIT()
262 #define __STREXB(value, ptr) __strex(value, ptr) argument
274 #define __STREXH(value, ptr) __strex(value, ptr) argument
286 #define __STREXW(value, ptr) __strex(value, ptr) argument
373 #define __STRBT(value, ptr) __strt(value, ptr) argument
383 #define __STRHT(value, ptr) __strt(value, ptr) argument
393 #define __STRT(value, ptr) __strt(value, ptr) argument
566 #define __BKPT(value) __ASM volatile ("bkpt "#value) argument
[all …]
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dicm.h76 #define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)) argument
85 #define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)) argument
184 #define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)) argument
187 #define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)) argument
190 #define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)) argument
193 #define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)) argument
196 #define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)) argument
199 #define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)) argument
226 #define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)) argument
229 #define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)) argument
[all …]
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dicm.h76 #define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)) argument
85 #define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)) argument
184 #define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)) argument
187 #define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)) argument
190 #define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)) argument
193 #define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)) argument
196 #define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)) argument
199 #define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)) argument
226 #define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)) argument
229 #define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)) argument
[all …]

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