| /bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/ |
| A D | hal_comp.c | 46 *(vu32*)(COMP_BASE + selection) = 0; in COMP_DeInit()
69 *(vu32*)(COMP_BASE + selection) = init_struct->Invert | in COMP_Init()
113 (state) ? (*(vu32*)(COMP_BASE + selection) |= COMP_CSR_EN) : in COMP_Cmd()
114 (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_EN); in COMP_Cmd()
147 (*(vu32*)(COMP_BASE + selection) |= COMP_CSR_COMPSW1) : in COMP_SwitchCmd()
148 (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_COMPSW1); in COMP_SwitchCmd()
170 return (((*(vu32*)(COMP_BASE + selection) & COMP_CSR_STA) != 0) ? in COMP_GetOutputLevel()
183 *(vu32*)(COMP_BASE + selection) |= COMP_CSR_LOCK; in COMP_LockConfig()
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| A D | hal_dma.c | 55 if((*(vu32*)&channel) >= (*(vu32*)DMA2_Channel1_BASE)) { in DMA_DeInit()
56 DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); in DMA_DeInit()
59 DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); in DMA_DeInit()
308 DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); in exDMA_ClearITPendingBit()
312 DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5); in exDMA_ClearITPendingBit()
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| A D | hal_ver.c | 102 return(READ_REG(*((vu32*)UID_BASE))); in Get_ChipsetUIDw0()
111 return(READ_REG(*((vu32*)(UID_BASE + 4U)))); in Get_ChipsetUIDw1()
120 return(READ_REG(*((vu32*)(UID_BASE + 8U)))); in Get_ChipsetUIDw2()
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| A D | hal_adc.c | 46 switch (*(vu32*)&adc) { in ADC_DeInit()
226 return (*(vu32*)ADC1_BASE); in ADC_GetDualModeConversionValue()
521 value = (*(vu32*)(*(vu32*)&adc + 0xB0 + off_addr)) - (*(vu32*)(*(vu32*)&adc + 0x7C + off_addr)); in ADC_GetInjectedConversionValue()
543 *(vu32*)(*(vu32*)&adc + 0x7C + off_addr) = value; in ADC_SetInjectedOffset()
555 return (u16)(*(vu32*) ((u32)adc + 0x18 + ((u32)channel << 2))); in ADC_GetChannelConvertedValue()
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| A D | hal_dac.c | 176 return (*(vu32*)(DAC_BASE + DOR_Offset + (channel >> 2))); in DAC_GetDataOutputValue()
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| A D | hal_gpio.c | 49 switch (*(vu32*)&gpio) { in GPIO_DeInit()
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| A D | hal_rcc.c | 820 switch (*(vu32*)&peripheral) { in RCC_ADC_ClockCmd()
927 switch (*(vu32*)&peripheral) { in RCC_GPIO_ClockCmd()
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| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ |
| A D | ht32f5xxxx_tm.c | 223 vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + OutInit->Channel; in TM_OutputInit()
224 vu32 *pCcr = (vu32*)&TMx->CH0CCR + OutInit->Channel; in TM_OutputInit()
225 vu32 *pAcr = (vu32*)&TMx->CH0ACR + OutInit->Channel; in TM_OutputInit()
883 vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; in TM_CHCCRPreloadConfig()
922 vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel;
993 vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; in TM_ImmActiveConfig()
1078 vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; in TM_OutputModeConfig()
1326 vu32* pCHnCCR = ((vu32*)&TMx->CH0CCR) + (TM_CH_n * 1); in TM_SetCaptureCompare()
1355 vu32* pCHnACR = ((vu32*)&TMx->CH0ACR) + (TM_CH_n * 1); in TM_SetAsymmetricCompare()
1384 vu32 *pIcfr = (vu32*)&TMx->CH0ICFR + Channel; in TM_CHPSCConfig()
[all …]
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| A D | ht32_serial.c | 53 static vu32 uReadIndex;
54 static vu32 uWriteIndex;
189 static vu32 uReadIndex;
190 static vu32 uWriteIndex;
191 static vu32 uDTRState = 0;
192 static vu32 gIsINEmpty = TRUE;
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| A D | ht32f5xxxx_tkey.c | 606 *(vu32*)((u32)&TKMx->K3CPR + ((3 - Key) * 4)) = Value; in TKM_SetKeyCapacitor()
623 return *(vu32*)((u32)&TKMx->K3CPR + ((3 - Key) * 4)); in TKM_GetKeyCapacitor()
655 return *(vu32*)((u32)&TKMx->K3CNTR + ((3 - Key) * 4)); in TKM_GetKeyCounterValue()
673 *(vu32*)((u32)&TKMx->K3THR + ((3 - Key) * 4)) = Value; in TKM_SetKeyThreshold()
690 return *(vu32*)((u32)&TKMx->K3THR + ((3 - Key) * 4)); in TKEY_GetKeyThreshold()
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| A D | ht32_retarget.c | 67 #define ITM_PORT32(n) (*((vu32 *)(0xE0000000 + 4 * n)))
69 #define DEMCR (*((vu32 *)(0xE000EDFC)))
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| A D | ht32f5xxxx_gpio.c | 630 vu32* pGPxCFGR = ((vu32*)&HT_AFIO->GPACFGR[0]) + GPIO_Px * 2; in AFIO_GPxConfig()
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| /bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ |
| A D | ht32f1xxxx_tm.c | 193 vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + OutInit->Channel; in TM_OutputInit()
194 vu32 *pCcr = (vu32*)&TMx->CH0CCR + OutInit->Channel; in TM_OutputInit()
195 vu32 *pAcr = (vu32*)&TMx->CH0ACR + OutInit->Channel; in TM_OutputInit()
786 vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; in TM_CHCCRPreloadConfig()
818 vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; in TM_ClearOREFConfig()
880 vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; in TM_ImmActiveConfig()
950 vu32 *pOcfr = (vu32*)&TMx->CH0OCFR + Channel; in TM_OutputModeConfig()
1177 vu32* pCHnCCR = ((vu32*)&TMx->CH0CCR) + (TM_CH_n * 1); in TM_SetCaptureCompare()
1200 vu32* pCHnACR = ((vu32*)&TMx->CH0ACR) + (TM_CH_n * 1); in TM_SetAsymmetricCompare()
1229 vu32 *pIcfr = (vu32*)&TMx->CH0ICFR + Channel; in TM_CHPSCConfig()
[all …]
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| A D | ht32_serial.c | 53 static vu32 uReadIndex;
54 static vu32 uWriteIndex;
194 static vu32 uReadIndex;
195 static vu32 uWriteIndex;
196 static vu32 uDTRState = 0;
197 static vu32 gIsINEmpty = TRUE;
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| A D | ht32_retarget.c | 67 #define ITM_PORT32(n) (*((vu32 *)(0xE0000000 + 4 * n)))
69 #define DEMCR (*((vu32 *)(0xE000EDFC)))
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| A D | ht32f1xxxx_gpio.c | 597 vu32* pGPxCFGR = ((vu32*)&HT_AFIO->GPACFGR[0]) + GPIO_Px * 2; in AFIO_GPxConfig()
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| /bsp/nuvoton/libraries/m460/rtt_port/ |
| A D | drv_sys.h | 19 vu32 vu32RegAddr;
20 vu32 vu32BitMask;
21 vu32 vu32Value;
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| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/ |
| A D | ht32f5xxxx_usbd.h | 106 vu32 EPBUFA: 10;
107 vu32 EPLEN : 10;
108 vu32 _RES0 : 3;
109 vu32 SDBS : 1;
110 vu32 EPADR : 4;
111 vu32 EPDIR : 1;
112 vu32 EPTYPE: 1;
113 vu32 _RES1 : 1;
114 vu32 EPEN : 1;
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| /bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/ |
| A D | ht32f1xxxx_usbd.h | 92 vu32 EPBUFA: 10;
93 vu32 EPLEN : 10;
94 vu32 _RES0 : 3;
95 vu32 SDBS : 1;
96 vu32 EPADR : 4;
97 vu32 EPDIR : 1;
98 vu32 EPTYPE: 1;
99 vu32 _RES1 : 1;
100 vu32 EPEN : 1;
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| /bsp/nuvoton/libraries/ma35/rtt_port/ |
| A D | drv_sys.h | 26 vu32 vu32RegAddr;
28 vu32 vu32BitMask;
30 vu32 vu32Value;
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| A D | drv_sys.c | 88 vu32 vc32RegValue = *((vu32 *)psNuReg->vu32RegAddr); in nu_sys_check_register()
89 vu32 vc32BMValue = vc32RegValue & psNuReg->vu32BitMask; in nu_sys_check_register()
167 uint32_t u32ChipCfg = *((vu32 *)REG_SYS_CHIPCFG); in nu_chipcfg_ddrsize()
174 uint32_t u32ChipCfg = *((vu32 *)REG_SYS_CHIPCFG); in nu_chipcfg_dump()
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| /bsp/w60x/drivers/ |
| A D | drv_standby.c | 23 typedef volatile unsigned long vu32; typedef
24 #define M32(adr) (*((vu32*) (adr)))
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| /bsp/mm32f327x/Libraries/MM32F327x/Include/ |
| A D | types.h | 62 typedef volatile unsigned int vu32; typedef
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| /bsp/nuvoton/libraries/nu_packages/Demo/ |
| A D | wormhole_demo.c | 114 *((vu32 *)req->msg.u32Addr0) = req->msg.u32Addr1; in proc_msg()
124 resp->msg.u32Addr0 = *((vu32 *)req->msg.u32Addr0); in proc_msg()
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| /bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Include/ |
| A D | ht32f1xxxx_01.h | 275 typedef __IO u32 vu32; typedef
354 #define ResetBit_BB(Addr, BitNumber) (*(vu32 *) ((Addr & 0xF0000000) + 0x02000000 + \
356 #define SetBit_BB(Addr, BitNumber) (*(vu32 *) ((Addr & 0xF0000000) + 0x02000000 + \
358 #define GetBit_BB(Addr, BitNumber) (*(vu32 *) ((Addr & 0xF0000000) + 0x02000000 + \
360 #define BitBand(Addr, BitNumber) (*(vu32 *) ((Addr & 0xF0000000) + 0x02000000 + \
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