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Searched refs:writew (Results 1 – 20 of 20) sorted by relevance

/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/
A Dhal_timer_irq.c35 writew (0,(uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CFG_LO_OFFSET)); in timer_irq_disable()
36 writew (0,(uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CFG_HI_OFFSET)); in timer_irq_disable()
56 writew(0xc000000f,(uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CFG_LO_OFFSET)); in timer_irq_init()
58 writew(TIMER_CFG_LO_ENABLE_MASK | TIMER_CFG_LO_RESET_MASK | in timer_irq_init()
72 writew(1, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_RESET_LO_OFFSET)); in timer_irq_set_timeout()
73 writew(ticks, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CMP_LO_OFFSET)); in timer_irq_set_timeout()
74 writew(1, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_RESET_HI_OFFSET)); in timer_irq_set_timeout()
A Dhal_gpio_pulp.c44 writew(val << pad_shift, pad_conf_reg); in gpio_pin_conf_pad()
64 writew(pads, (uintptr_t)(PULP_GPIO_ADDR + GPIO_PADDIR_OFFSET)); in gpio_pin_configure()
76 writew(en, (uintptr_t)(PULP_GPIO_ADDR + GPIO_GPIOEN_OFFSET)); in gpio_pin_configure()
95 writew((outval & ~mask) | (value & mask), in gpio_port_set_masked_raw()
105 writew(outval | mask, (uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET)); in gpio_port_set_bits_raw()
114 writew(outval & ~mask, in gpio_port_clear_bits_raw()
124 writew(outval ^ mask, (uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET)); in gpio_port_toggle_bits()
A Dhal_irq.c31 writew(mask, (uintptr_t)(PULP_FC_IRQ_ADDR + IRQ_REG_MASK_OFFSET)); in irq_mask()
36 writew(mask, (uintptr_t)(PULP_FC_IRQ_ADDR + IRQ_REG_MASK_SET_OFFSET)); in irq_enable()
41 writew(mask, (uintptr_t)(PULP_FC_IRQ_ADDR + IRQ_REG_MASK_CLEAR_OFFSET)); in irq_disable()
A Dhal_fll.c118 writew(reg2.raw, (uintptr_t)(PULP_FLL_ADDR + FLL_CONF2_OFFSET + in __fll_init()
150 writew(reg_int.raw, in __fll_init()
157 writew(reg1.raw, (uintptr_t)(PULP_FLL_ADDR + FLL_CONF1_OFFSET + in __fll_init()
202 writew(reg1.raw, (uintptr_t)(PULP_FLL_ADDR + FLL_CONF1_OFFSET + in __rt_fll_set_freq()
A Dhal_soc_eu.c29 writew(mask, (uintptr_t)(SOC_EU_ADDR + offset)); in soc_eu_mask_set()
A Dhal_pinmux1.c39 writew((func & 0x3) << padfun_shift, padfun_reg); in pinmux_pin_set()
/bsp/cvitek/drivers/libraries/
A Dmmio.h40 #define writew(v, c) ({ __io_bw(); __raw_writew((v), (c)); __io_aw(); }) macro
65 #define writew(v, a) __raw_writew(v,a) macro
70 #define cpu_write16(a, v) writew(a, v)
89 writew(value, (void *) addr); in mmio_write_16()
146 #define iowrite16 writew
/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/
A Dhal_soc_eu_periph.h107 writew(val, (uintptr_t)(SOC_EU_ADDR + SOC_FC_MASK0_OFFSET + reg)); in soc_eu_fc_write()
117 writew(val, (uintptr_t)(SOC_EU_ADDR + SOC_CL_MASK0_OFFSET + reg)); in soc_eu_cl_write()
127 writew(val, (uintptr_t)(SOC_EU_ADDR + SOC_PR_MASK0_OFFSET + reg)); in soc_eu_pr_write()
191 writew(mask, (uintptr_t)(SOC_EU_ADDR + SOC_EVENT_OFFSET)); in hal_soc_eu_set_mask()
/bsp/at91/at91sam9g45/platform/
A Dio.h21 #define writew(v,a) (*(volatile unsigned short *)(a) = (v)) macro
/bsp/allwinner/libraries/sunxi-hal/hal/source/regulator/
A Dtype.h20 #define writew(v, addr) (*((volatile unsigned short *)(long)(addr)) = (unsigned short)(v)) macro
/bsp/at91/at91sam9260/platform/
A Dio.h23 #define writew(v,a) (*(volatile unsigned short *)(a) = (v)) macro
/bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/
A Dpulp_io.h43 static inline void writew(uint32_t val, uintptr_t addr) in writew() function
A Dcore_pulp.h1176 writew(1UL << IRQn, (uintptr_t)(FC_IRQ_ADDR + IRQ_REG_MASK_SET_OFFSET)); in __irq_enable()
1206 writew(1UL << IRQn, (uintptr_t)(FC_IRQ_ADDR + IRQ_REG_MASK_CLEAR_OFFSET)); in __irq_disable()
1234 writew(1UL << IRQn,(uintptr_t)(FC_IRQ_ADDR + IRQ_REG_INT_SET_OFFSET)); in __irq_set_pending()
1246 writew(1UL << IRQn,(uintptr_t)(FC_IRQ_ADDR + IRQ_REG_INT_CLEAR_OFFSET)); in __irq_clear_pending()
/bsp/zynqmp-a53-dfzu2eg/drivers/zynqmp/
A Dzynqmp_reg.h22 #define writew(data, reg) ((*((volatile unsigned short *)(reg))) = (unsigned short)(data)) macro
/bsp/avr32/software_framework/utils/libs/newlib_addons/include/
A Dnlao_io.h68 #define writew(v,a) __raw_writew(v,a) macro
/bsp/dm365/platform/
A Ddm36x.h179 #define writew(v,a) davinci_writew(v,a) macro
/bsp/raspberry-pi/raspi-dm2.0/drivers/sdhci/include/
A Dsdhci.h697 #define writew(v, c) rt_uint16_t_write(v, c) macro
716 writew(val, host->ioaddr + reg); in sdhci_writew()
/bsp/dm365/drivers/
A Dspi-davinci.c253 writew(spidat1, dspi->base + SPIDAT1 + 2); in davinci_spi_chipselect()
675 writew(spidat1 >> 16, dspi->base + SPIDAT1 + 2); in davinci_spi_bufs()
/bsp/k230/drivers/interdrv/sdio/
A Ddrv_sdhci.c107 writew((uint16_t)val, (void*)host->mapbase + reg); in sdhci_writew()
/bsp/allwinner/libraries/sunxi-hal/hal/source/sdmmc/
A Dhal_sdhost.c230 writew((value), (uint32_t)(host)->reg_base + reg);\
257 writew((value), HAL_PT_TO_U((host)->reg_base) + reg)

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