Searched refs:GICD_CTLR (Results 1 – 2 of 2) sorted by relevance
81 while ((HWREG32(base + GICD_CTLR) & rwp_bit)) in gicv3_wait_for_rwp()225 HWREG32(base + GICD_CTLR) = 0; in gicv3_dist_init()255 HWREG32(base + GICD_CTLR) = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1; in gicv3_dist_init()
27 #define GICD_CTLR 0x0000 macro
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