1 /* 2 * Copyright (c) 2022-2024, Artinchip Technology Co., Ltd 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __USB_DC_AIC_REG_H__ 8 #define __USB_DC_AIC_REG_H__ 9 10 #define __IO volatile /*!< Defines 'read / write' permissions */ 11 12 typedef struct { 13 __IO uint32_t ahbbasic; /* 0x0000: AHBBASIC */ 14 __IO uint32_t usbdevinit; /* 0x0004: USBDEVINIT */ 15 __IO uint32_t usbphyif; /* 0x0008: USBPHYIF */ 16 __IO uint32_t usbulpiphy; /* 0x000C: USBULPIPHY */ 17 __IO uint32_t usbintsts; /* 0x0010: USBINTSTS */ 18 __IO uint32_t usbintmsk; /* 0x0014: USBINTMSK */ 19 __IO uint32_t rxfifosiz; /* 0x0018: RXFIFOSIZ */ 20 __IO uint32_t rxfifosts_pop; /* 0x001C: RXFIFOSTS pop */ 21 __IO uint32_t nptxfifosiz; /* 0x0020: NPTXFIFOSIZ */ 22 __IO uint32_t nptxfifosts; /* 0x0024: NPTXFIFOSTS */ 23 __IO uint32_t txfifosiz[2]; /* 0x0028 - 0x002C: TXFIFOSIZ() */ 24 __IO uint32_t rxfifosts_dbg; /* 0x0030: RXFIFOSTS_DBG */ 25 uint8_t res0[0x1cc]; 26 __IO uint32_t usbdevconf; /* 0x0200: USBDEVCONF */ 27 __IO uint32_t usbdevfunc; /* 0x0204: USBDEVFUNC */ 28 __IO uint32_t usblinests; /* 0x0208: USBLINESTS */ 29 __IO uint32_t inepintmsk; /* 0x020C: INEPINTMSK */ 30 __IO uint32_t outepintmsk; /* 0x0210: OUTEPINTMSK */ 31 __IO uint32_t usbepint; /* 0x0214: USBEPINT */ 32 __IO uint32_t usbepintmsk; /* 0x0218: USBEPINTMSK */ 33 uint8_t res1[4]; 34 __IO uint32_t inepcfg[5]; /* 0x0220 - 0x0230: INEPCFG() */ 35 uint8_t res2[0xc]; 36 __IO uint32_t outepcfg[5]; /* 0x0240 - 0x0250: OUTEPCFG() */ 37 uint8_t res3[0xc]; 38 __IO uint32_t inepint[5]; /* 0x0260 - 0x0270: INEPINT() */ 39 uint8_t res4[0xc]; 40 __IO uint32_t outepint[5]; /* 0x0280 - 0x0290: OUTEPINT() */ 41 uint8_t res5[0xc]; 42 __IO uint32_t ineptsfsiz[5]; /* 0x02A0 - 0x02B0: INEPTSFSIZ() */ 43 uint8_t res6[0xc]; 44 __IO uint32_t outeptsfsiz[5]; /* 0x02C0 - 0x02D0: OUTEPTSFSIZ() */ 45 uint8_t res7[0x2c]; 46 __IO uint32_t inepdmaaddr[5]; /* 0x0300 - 0x0310: INEPDMAADDR() */ 47 uint8_t res8[0xc]; 48 __IO uint32_t outepdmaaddr[5]; /* 0x0320 - 0x0330: OUTEPDMAADDR() */ 49 uint8_t res9[0xc]; 50 __IO uint32_t ineptxsts[5]; /* 0x0340 - 0x0350: INEPTXSTS() */ 51 uint8_t res10[0xc]; 52 __IO uint32_t dtknqr1; /* 0x0360: DTKNQR1 */ 53 __IO uint32_t dtknqr2; /* 0x0364: DTKNQR2 */ 54 __IO uint32_t dtknqr3; /* 0x0368: DTKNQR3 */ 55 __IO uint32_t dtknqr4; /* 0x036C: DTKNQR4 */ 56 }AIC_UDC_RegDef; 57 58 /*===================================================================== */ 59 /*definitions related to CSR setting */ 60 61 /* AHBBASIC */ 62 #define AHBBASIC_NOTI_ALL_DMA_WRIT (1 << 8) 63 #define AHBBASIC_REM_MEM_SUPP (1 << 7) 64 #define AHBBASIC_INV_DESC_ENDIANNESS (1 << 6) 65 #define AHBBASIC_AHB_SINGLE (1 << 5) 66 #define AHBBASIC_TXENDDELAY (1 << 3) 67 #define AHBBASIC_AHBIDLE (1 << 2) 68 #define AHBBASIC_DMAREQ (1 << 1) 69 70 /* USBDEVINIT */ 71 #define USBDEVINIT_HBSTLEN_MASK (0xf << 12) 72 #define USBDEVINIT_HBSTLEN_SHIFT 12 73 #define USBDEVINIT_HBSTLEN_SINGLE 0 74 #define USBDEVINIT_HBSTLEN_INCR 1 75 #define USBDEVINIT_HBSTLEN_INCR4 3 76 #define USBDEVINIT_HBSTLEN_INCR8 5 77 #define USBDEVINIT_HBSTLEN_INCR16 7 78 #define USBDEVINIT_DMA_EN (1 << 11) 79 #define USBDEVINIT_NP_TXF_EMP_LVL (1 << 10) 80 #define USBDEVINIT_GLBL_INTR_EN (1 << 9) 81 #define USBDEVINIT_CTRL_MASK (USBDEVINIT_NP_TXF_EMP_LVL | \ 82 USBDEVINIT_DMA_EN | \ 83 USBDEVINIT_GLBL_INTR_EN) 84 #define USBDEVINIT_IN_TKNQ_FLSH (1 << 8) 85 #define USBDEVINIT_TXFNUM_MASK (0x1f << 3) 86 #define USBDEVINIT_TXFNUM_SHIFT 3 87 #define USBDEVINIT_TXFNUM_LIMIT 0x1f 88 #define USBDEVINIT_TXFNUM(_x) ((_x) << 3) 89 #define USBDEVINIT_TXFFLSH (1 << 2) 90 #define USBDEVINIT_RXFFLSH (1 << 1) 91 #define USBDEVINIT_CSFTRST (1 << 0) 92 93 /* USBPHYIF */ 94 #define USBPHYIF_ULPI_CLK_SUSP_M (1 << 19) 95 #define USBPHYIF_ULPI_AUTO_RES (1 << 18) 96 #define USBPHYIF_PHY_LP_CLK_SEL (1 << 15) 97 #define USBPHYIF_USBTRDTIM_MASK (0xf << 10) 98 #define USBPHYIF_USBTRDTIM_SHIFT 10 99 #ifndef USBPHYIF_HS_TRDT_VALUE 100 #define USBPHYIF_HS_TRDT_VALUE 9U 101 #endif /* USBD_HS_TRDT_VALUE */ 102 #ifndef USBPHYIF_FS_TRDT_VALUE 103 #define USBPHYIF_FS_TRDT_VALUE 5U 104 #define USBPHYIF_DEFAULT_TRDT_VALUE 9U 105 #endif /* USBD_HS_TRDT_VALUE */ 106 #define USBPHYIF_DDRSEL (1 << 7) 107 #define USBPHYIF_ULPI_UTMI_SEL (1 << 4) 108 #define USBPHYIF_PHYIF16 (1 << 3) 109 #define USBPHYIF_PHYIF8 (0 << 3) 110 #define USBPHYIF_TOUTCAL_MASK (0x7 << 0) 111 #define USBPHYIF_TOUTCAL_SHIFT 0 112 #define USBPHYIF_TOUTCAL_LIMIT 0x7 113 #define USBPHYIF_TOUTCAL(_x) ((_x) << 0) 114 115 /* USBINTSTS/USBINTMSK interrupt register */ 116 #define INT_RESUME (1u << 31) 117 #define INT_INCOMP_ISO_OUT_INT (0x1 << 21) 118 #define INT_INCOMP_ISO_IN_INT (0x1 << 20) 119 #define INT_OUT_EP (0x1 << 19) 120 #define INT_IN_EP (0x1 << 18) 121 #define INT_ENUMDONE (0x1 << 13) 122 #define INT_RESET (0x1 << 12) 123 #define INT_SUSPEND (0x1 << 11) 124 #define INT_EARLY_SUSPEND (0x1 << 10) 125 #define INT_GOUTNAKEFF (0x1 << 7) 126 #define INT_GINNAKEFF (0x1 << 6) 127 #define INT_NP_TX_FIFO_EMPTY (0x1 << 5) 128 #define INT_RX_FIFO_NOT_EMPTY (0x1 << 4) 129 #define INT_SOF (0x1 << 3) 130 131 #define FULL_SPEED_CONTROL_PKT_SIZE 8 132 #define FULL_SPEED_BULK_PKT_SIZE 64 133 134 #define HIGH_SPEED_CONTROL_PKT_SIZE 64 135 #define HIGH_SPEED_BULK_PKT_SIZE 512 136 137 #define RX_FIFO_SIZE (1024) 138 #define NPTX_FIFO_SIZE (1024) 139 #define PTX_FIFO_SIZE (384) 140 141 /* fifo size configure */ 142 #define EPS_NUM 5 143 #define PERIOD_IN_EP_NUM 2 144 #define TOTAL_FIFO_SIZE 0x3f6 145 #ifdef LPKG_CHERRYUSB_DEVICE_VIDEO_DVP_TEMPLATE 146 /* video_dvp_template must use 2K Bytes period_tx_fifo */ 147 #define AIC_RX_FIFO_SIZE 0x99 148 #define AIC_NP_TX_FIFO_SIZE 0x100 149 #define AIC_PERIOD_TX_FIFO1_SIZE 0x200 150 #define AIC_PERIOD_TX_FIFO2_SIZE 0x0 151 #else 152 /* default configuration */ 153 #define AIC_RX_FIFO_SIZE 0x119 154 #define AIC_NP_TX_FIFO_SIZE 0x100 155 #define AIC_PERIOD_TX_FIFO1_SIZE 0x100 156 #define AIC_PERIOD_TX_FIFO2_SIZE 0xDD 157 #endif 158 159 #define DEPCTL_TXFNUM_0 (0x0 << 22) 160 #define DEPCTL_TXFNUM_1 (0x1 << 22) 161 #define DEPCTL_TXFNUM_2 (0x2 << 22) 162 #define DEPCTL_TXFNUM_3 (0x3 << 22) 163 #define DEPCTL_TXFNUM_4 (0x4 << 22) 164 165 /* RXFIFOSTS */ 166 #define RXFIFOSTS_EPNUM_MASK (0xFU << 0) 167 #define RXFIFOSTS_BCNT_MASK (0x7FFU << 4) 168 #define RXFIFOSTS_DPID_MASK (0x3U << 15) 169 #define RXFIFOSTS_PKTSTS_SHIFT (17) 170 #define RXFIFOSTS_PKTSTS_MASK (0xFU << RXFIFOSTS_PKTSTS_SHIFT) 171 #define PKTSTS_GLOBAL_OUT_NAK (0x1 << RXFIFOSTS_PKTSTS_SHIFT) 172 #define PKTSTS_OUT_DATA_PKT_REC (0x2 << RXFIFOSTS_PKTSTS_SHIFT) 173 #define PKTSTS_OUT_TRANSFER_COMP (0x3 << RXFIFOSTS_PKTSTS_SHIFT) 174 #define PKTSTS_SETUP_TRANSACTION_COMP (0x4 << RXFIFOSTS_PKTSTS_SHIFT) 175 #define PKTSTS_SETUP_DATA_PKT_REC (0x6 << RXFIFOSTS_PKTSTS_SHIFT) 176 #define RXFIFOSTS_FN_MASK (0xFU << 21) 177 178 /* USBDEVCONF */ 179 #define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0) 180 #define DEV_SPEED_FULL_SPEED_20 (0x1 << 0) 181 #define DEV_SPEED_LOW_SPEED_11 (0x2 << 0) 182 #define DEV_SPEED_FULL_SPEED_11 (0x3 << 0) 183 #define EP_MISS_CNT(x) (x << 18) 184 #define DEVICE_ADDRESS_MASK (0x7F << 4) 185 #define DEVICE_ADDRESS(x) (x << 4) 186 #define PERIOD_FRAME_INTERVAL_80 (0 << 11) 187 #define PERIOD_FRAME_INTERVAL_85 (1 << 11) 188 #define PERIOD_FRAME_INTERVAL_90 (2 << 11) 189 #define PERIOD_FRAME_INTERVAL_95 (3 << 11) 190 191 /* USBDEVFUNC */ 192 #define NORMAL_OPERATION (0x1 << 0) 193 #define SOFT_DISCONNECT (0x1 << 1) 194 #define USBDEVFUNC_SERVICE_INTERVAL_SUPPORTED (1 << 19) 195 #define USBDEVFUNC_PWRONPRGDONE (1 << 11) 196 #define USBDEVFUNC_CGOUTNAK (1 << 10) 197 #define USBDEVFUNC_SGOUTNAK (1 << 9) 198 #define USBDEVFUNC_CGNPINNAK (1 << 8) 199 #define USBDEVFUNC_SGNPINNAK (1 << 7) 200 #define USBDEVFUNC_TSTCTL_MASK (0x7 << 4) 201 #define USBDEVFUNC_TSTCTL_SHIFT (4) 202 #define USBDEVFUNC_GOUTNAKSTS (1 << 3) 203 #define USBDEVFUNC_GNPINNAKSTS (1 << 2) 204 #define USBDEVFUNC_SFTDISCON (1 << 1) 205 #define USBDEVFUNC_RMTWKUPSIG (1 << 0) 206 207 /* USBLINESTS: Enumeration speed */ 208 #define USB_ENUM_SPEED_SHIFT 1 209 #define USB_ENUM_SPEED_MASK (0x3 << USB_ENUM_SPEED_SHIFT) 210 #define USB_ENUM_SPEED_HIGH 0 211 #define USB_ENUM_SPEED_FULL 1 212 #define USB_HIGH_30_60MHZ (0x0 << USB_ENUM_SPEED_SHIFT) 213 #define USB_FULL_30_60MHZ (0x1 << USB_ENUM_SPEED_SHIFT) 214 #define USB_LOW_6MHZ (0x2 << USB_ENUM_SPEED_SHIFT) 215 #define USB_FULL_48MHZ (0x3 << USB_ENUM_SPEED_SHIFT) 216 217 /* USBEPINT endpoint interrupt register */ 218 #define DAINT_OUT_BIT (16) 219 #define DAINT_IN_MASK (0xFFFF) 220 #define DAINT_OUT_MASK (0xFFFFU << DAINT_OUT_BIT) 221 222 /* INEPCFG()/OUTEPCFG() 223 * devicecontrol IN/OUT endpoint 0 control register 224 */ 225 #define DEPCTL_EPENA (1u << 31) 226 #define DEPCTL_EPDIS (0x1 << 30) 227 #define DEPCTL_SETD1PID (0x1 << 29) 228 #define DEPCTL_SETD0PID (0x1 << 28) 229 #define DEPCTL_SNAK (0x1 << 27) 230 #define DEPCTL_CNAK (0x1 << 26) 231 #define DEPCTL_TXFIFONUM_SHIFT 22 232 #define DEPCTL_TXFIFONUM_MASK (0xF << 22) 233 #define DEPCTL_STALL (0x1 << 21) 234 #define DEPCTL_TYPE_BIT (18) 235 #define DEPCTL_TYPE_MASK (0x3 << 18) 236 #define DEPCTL_CTRL_TYPE (0x0 << 18) 237 #define DEPCTL_ISO_TYPE (0x1 << 18) 238 #define DEPCTL_BULK_TYPE (0x2 << 18) 239 #define DEPCTL_INTR_TYPE (0x3 << 18) 240 #define DEPCTL_USBACTEP (0x1 << 15) 241 #define DEPCTL_NEXT_EP_BIT (11) 242 #define DEPCTL_NEXT_EP_MASK (0xFU << DEPCTL_NEXT_EP_BIT) 243 #define DEPCTL_MPS_BIT (0) 244 #define DEPCTL_MPS_MASK (0x7FF) 245 246 #define DEPCTL0_MPS_64 (0x0 << 0) 247 #define DEPCTL0_MPS_32 (0x1 << 0) 248 #define DEPCTL0_MPS_16 (0x2 << 0) 249 #define DEPCTL0_MPS_8 (0x3 << 0) 250 #define DEPCTL_MPS_BULK_512 (512 << 0) 251 #define DEPCTL_MPS_INT_MPS_16 (16 << 0) 252 253 #define DIEPCTL0_NEXT_EP_BIT (11) 254 255 /* INEPINT/OUTEPINT device IN/OUT endpoint interrupt register */ 256 #define CTRL_OUT_EP_SETUP_RCVD (0x1 << 15) 257 #define TXFIFO_EMP_INT (0x1 << 7) 258 #define INEP_NAKEFF (0x1 << 6) 259 #define BACK2BACK_SETUP_RECEIVED (0x1 << 6) 260 #define CTRL_OUT_EP_STATUS_PHASE_RCVD (0x1 << 5) 261 #define INTKNEPMIS (0x1 << 5) 262 #define INTKN_TXFEMP (0x1 << 4) 263 #define NON_ISO_IN_EP_TIMEOUT (0x1 << 3) 264 #define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1 << 3) 265 #define AHB_ERROR (0x1 << 2) 266 #define EPDISBLD (0x1 << 1) 267 #define TRANSFER_DONE (0x1 << 0) 268 269 /* Masks definitions */ 270 #define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\ 271 | INT_RESET | INT_SUSPEND) 272 #define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE |\ 273 AHB_ERROR | TRANSFER_DONE) 274 #define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT | AHB_ERROR | TRANSFER_DONE) 275 #define GAHBCFG_INIT (USBDEVINIT_DMA_EN | USBDEVINIT_GLBL_INTR_EN\ 276 | (USBDEVINIT_HBSTLEN_INCR4 <<\ 277 USBDEVINIT_HBSTLEN_SHIFT)) 278 279 /* INEPTSFSIZ/OUTEPTSFSIZ */ 280 #define DXEPTSIZ_MULCNT_SHIFT 29 281 #define DXEPTSIZ_MULCNT_MASK (0x3U << DXEPTSIZ_MULCNT_SHIFT) 282 #define DXEPTSIZ_PKT_CNT_SHIFT 19 283 #define DXEPTSIZ_PKT_CNT_MASK (0x3FFU << DXEPTSIZ_PKT_CNT_SHIFT) 284 #define DXEPTSIZ_XFER_SIZE_SHIFT 0 285 #define DXEPTSIZ_XFER_SIZE_MASK (0x7FFFFU << DXEPTSIZ_XFER_SIZE_SHIFT) 286 287 /* Device Endpoint X Transfer Size Register INEPTSFSIZ() */ 288 #define DIEPT_SIZ_PKT_CNT(x) (x << 19) 289 #define DIEPT_SIZ_XFER_SIZE(x) (x << 0) 290 291 /* Device OUT Endpoint X Transfer Size Register OUTEPTSFSIZ() */ 292 #define DOEPT_SIZ_PKT_CNT(x) (x << 19) 293 #define DOEPT_SIZ_XFER_SIZE(x) (x << 0) 294 #define DOEPT_SIZ_XFER_SIZE_MAX_EP0 (0x7F << 0) 295 #define DOEPT_SIZ_XFER_SIZE_MAX_EP (0x7FFF << 0) 296 297 /* Device Endpoint-N Control Register INEPCFG()/OUTEPCFG() */ 298 #define DIEPCTL_TX_FIFO_NUM(x) (x << 22) 299 #define DIEPCTL_TX_FIFO_NUM_MASK (~DIEPCTL_TX_FIFO_NUM(0xF)) 300 301 /* Device ALL Endpoints Interrupt Register (USBEPINT) */ 302 #define DAINT_IN_EP_INT(x) (x << 0) 303 #define DAINT_OUT_EP_INT(x) (x << 16) 304 305 #define AIC_EP_FIFO_BASE 0x1000UL 306 #define AIC_EP_FIFO_SIZE 0x1000UL 307 308 /* In EPn Txfifo Status (INEPTXSTS) */ 309 #define INEPTXSTS_IN_EP_TXFIFO_STS (0xFFFFU << 0) 310 311 312 #endif 313